DesignConEast 2005 Track 4: Power and Packaging (4-WA1)

Transcription

1 DesignConEast 2005 Track 4: Power and Packaging (4-WA1) Design of a Low-Power Differential Repeater Using Low-Voltage Swing and Charge Recycling Authors: Brock J. LaMeres, University of Colorado / Sunil P. Khatri Texas A&M University 1

2 Problem Statement Power is the largest problem facing IC/SoC designers On-chip trace delay limits performance in DSM 1) Repeaters are used to reduce delay 2) Repeaters add power 2

3 Agenda 1) Problem Motivation 2) Proposed Solution 3) Simulation Results 3

4 Problem Motivation RC Trace Delay trc = (0.69) RC Rint Cint ρ 4

5 Problem Motivation RC Trace Delay Rint R C ρl = L A ε W L = t ox L trc L 2 Quadratic Increase Cint ρ L 5

6 Problem Motivation Interconnect Dominates DSM Performance Today 1959: First Integrated Circuit 1948: Elmore Delay Presented 2010: Nanometer technology (<0.05um) Interconnect Delay Negates Moore s Law 2000: Deep Sub Micron (<0.5um) Interconnect Delay Dominates Performance 1990: Gate Delay = Interconnect Delay (1um) Source: 2003 ITRS 6

7 Problem Motivation Standard Solution : Repeater Insertion L R/n 1 2 R/n n-1 R/n n C/n C/n C/n Break line into smaller segments: (L 0) Optimal sizing when: Linear dependence: t buf = t RC t delay L 7

8 Repeaters Add Power Problem Motivation R/n 1 2 R/n n-1 R/n n C/n C/n C/n P = C V f dynamic 2 swing Power (# of Repeaters) Pshort circuit = Isat VDD f 8

9 Problem Motivation Repeater Power Scaling Isn t Realistic R/n 1 2 R/n n-1 R/n n C/n C/n C/n 2003 ITRS Prediction: at 50nm, global interconnect will consume 40% of power in VLSI 0.25um up : 50,000 repeaters : 8 Watts 70nm up : 700,000 repeaters : 60 Watts 9

10 Need to Reduce Power Problem Motivation R/n 1 2 R/n n-1 R/n n C/n C/n C/n Need techniques to reduce power of repeater scheme A small decrease in delay is acceptable Net improvement in PDP is the goal 10

11 Proposed Solution Current Trends Differential signaling on clock traces for Noise Immunity - Well Suited for Low-Voltage Output Swing - Well Suited for Charge Sharing 11

12 Proposed Solution Differential Signaling Complimentary Outputs for VLSI CMOS Receiver Performs (CLK-CLK) which rejects coupled noise Receiver Performs (CLK-CLK) which doubles effective amplitude P N 12

13 Low-Voltage Swing Outputs Proposed Solution Reducing Output Swing Reduces Power P = C V f dynamic 2 swing Quadratic Decrease!!! Differential Signaling has extra margin to accommodate this (-) 13

14 Low-Voltage Swing Outputs Proposed Solution Typical CMOS swings from V SS to V DD Insert V t drops between supplies to reduce output swing + V t,n - + V t,p - 14

15 Low-Voltage Swing Outputs Proposed Solution The reduced output swing is: VLV swing = VDD Vt, n Vt, p + V t,n - The reduced power is: P = C V f 2 dynamic LV swing + V t,p - 15

16 Proposed Solution Charge Recycling Typical CMOS charges output from supply Q = 0 1 C load Vswing Q = 1 0 C load Vswing Cload Cload 0 1 Transition 1 0 Transition 16

17 Proposed Solution Charge Recycling The Symmetry of Differential Signaling can be exploited 0 1 Q p Q n One Driver is always charging while the other is discharging

18 Proposed Solution Charge Recycling During first half of the transition equal charge is distributed Discharging from V 1 to V swing /2 Q charge = -Q discharge Charging from V 0 to V swing /2 18

19 Proposed Solution Charge Recycling Charge can be Shared between & from t 0 to t Vswing/2 Discharging from V 1 to V swing /2 Q charge = -Q discharge Charging from V 0 to V swing /2 t 0 t Vswing/2 19

20 Proposed Solution Charge Recycling From t Vswing/2 to t SS charge is provided by Supplies as usual Charging from V swing /2 to V OH Discharging from V swing /2 to V OL t 0 t Vswing/2 t SS 20

21 Proposed Solution Charge Recycling & are connected from t 0 to t Vswing/2 0 1 Q share

22 Proposed Solution Charge Recycling & are disconnected from t Vswing/2 to t SS 0 1 Q supply Q supply

23 Proposed Solution Charge Recycling Circuit Description A B O

24 Simulation Results Trace Modeling BSIM 0.1um Process (BPTM) 1cm Length Metal 3 P N R trace = 1333Ω C trace = 1.29pF 24

25 Simulation Results Repeater Design R/n 1 2 R/n n-1 R/n n C/n C/n C/n Using Optimal Sizing: Full-Swing Repeater: 15 Low-Voltage Repeater: 9 Low-Voltage Charge Recycling Repeater: 9 25

26 Simulation Results Circuit Operation Circuit Operation 26

27 Current Profile vs. Time Simulation Results Full-Swing Low-Voltage LV Charge-Recycling 27

28 Simulation Results Performance Both Improve PDP Lowest Delay = Full-Swing Repeater Lowest PDP = Low-Voltage Repeater (32% improvement) Lowest Power = Low-Voltage Charge Recycling Repeater (43% improvement) 28

29 Implementation Details Suggested Use On-Chip Metal 3 or Greater Not Suggested On-Chip Metal 1 or 2 (too much resistance, acts distributed) Off-Chip (too much inductance, acts distributed) 29

30 Implementation Details Sizing -Low Resistance - Negligible Capacitance < (20%) τ load 30

31 Summary Trends Power and Delay are major problems in DSM Repeaters are expected to dominate power Differential signaling is being used for noise immunity on clocks Proposed Technique Low-Voltage Swing enabled by differential signaling Charge Recycling enabled by differential signaling Suffer small delay penalty for decreased power (PDP ) 31

32 Questions? 32