University of Toronto. Final Exam


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1 University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last page of test.. Calculator type unrestricted 3. Grading indicated by [ ]. Attempt all questions since a blank answer will certainly get 0. Question Mark Last Name: 6 Total First Name: Student #: (max grade = 36) page 1 of 9
2 [6] Question 1: Each correct answer is worth 0.5 marks. For the questions below, circle one of True [T] or False [F]. T F In the 1970 s and 1980 s, CMOS digital circuits became more popular than bipolar digital circuits due to their higher speed. T F Two ways to add dopants to a silicon substrate are ion implantation and injection. T F For the detailed MOS gate capacitance model, the gatebulk capacitance is 0 when the transistor is in triode. T F Channel length modulation of digital circuits is important as it reduces the speed of digital circuits. T F Elmore delay is not necessarily accurate in absolute prediction of an RC tree delay but if one minimizes the Elmore delay, generally, the RC tree delay is also minimized. T F Since dynamic gates precharge high then fall low during evaluation, a dynamic bus will never see twice the crosstalk capacitance due opposite switching during evaluation. T F It is not possible to make a symmetric CMOS 3input nand gate. T F Most flash memory is built as NOR memory architecture. T F Hot carrier injection is a selflimiting mechanism when putting electrons on a floating gate. T F A DRAM memory cell should be refreshed after every read of that cell. T F The pmos transistors in a SRAM memory cell generally do not affect read or write speed. T F Bitline twists are used in SRAM memory to reduce capacitance coupling and therefore increase memory speed. page of 9
3 [6] Question : Transistor equivalency says that that transistors in series having the same width is equivalent to a single transistor with that width and the lengths added together as shown below. For the case below (voltage, width and lengths shown), show that this is indeed true (not using transistor equivalency) by finding I D1 and I D3 and also find V 1. (Ignore body effect and finite output impedance). 3V 3V 3V V 1 I D1 W L W L 1 3V I D3 W L 3 = W ( L 1 + L ) W = 1µm L 1 = 0.5µm L = 0.5µm (transistor parameters on last page) page 3 of 9
4 [6] Question 3: Consider the d register shown below. D I 5 T 1 I 1 I I 6 T 3 I 3 I 4 Q CK I 7 I 8 T T 4 Assuming that each Tgate turns on/off according to it controlling signal edge, and defining the following delays: is the delay through the i th inverter T Ii T Gi T Ti is the delay through the i thtgate from its control input to its output is the delay through the i thtgate from its data input to its output a) Find T setup in terms of T Ii, T Gi and T Ti (be specific in terms of i ). b) Find T pcq in terms of T Ii, T Gi and T Ti (be specific in terms of i ). page 4 of 9
5 [6] Question 4: a) Explain why when a single logic signal is crossing from clock domain 1 to clock domain, the last logic element in clock domain 1 should be a register. Give an example where an error occurs if the last element is NOT a register. (Show a timing diagram in your example). b) A 3register synchronizer (1 register in clock domain 1 and 3 registers in clock domain ) uses registers with τ s = 500ps and t rd = 00ps. Assuming the input toggles at 10MHz, what is the minium clock period for which the mean time between failures is 1000 years? (Your clock period answer only needs to be accurate to 0%). page 5 of 9
6 [6] Question 5: A single CMOS inverter is sized with minimum transistor lengths of 0.5um, NMOS width of 1um and PMOS width of um. This inverter is driving a fixed capacitive load of 50fF. However, the output wire of the inverter also has 50fF capacitive coupling to another signalling wire which may or may not switch when the inverter switches. Estimate the fastest delay (either t dr or t df ) and slowest delay (either t dr or t df ) through the inverter taking into account the adjacent signalling wire. Use parameters on last page. page 6 of 9
7 [6] Question 6: a) An embedded SRAM contains bit words. If it is physically arranged in a square fashion, how many bits will be used in the row decode and how many bits will be used in the column decode? (assume the cell aspect ratio is square). b) A dynamic memory cell has a worst case leakage current of na (independent of voltage) and is refreshed every 100µs. If the power supply is 3V and the cell voltage should not leak lower than 1.8V, find the required cell capacitance value. c) In a DRAM memory, the sense amps are connected directly to the bit lines. In a SRAM memory, the sense amps are connected to the bit lines through isolation PMOS transistors. Explain why the isolation transistors are needed in an SRAM. Also, explain why the isolation transistors should NOT be used in a DRAM. page 7 of 9
8 (blank sheet for scratch calculations) page 8 of 9
9 ECE334 Digital Electronics Equation Sheet Constants: k = JK 1 ; q = C ; V T = kt q 6mV at 300 K; ε 0 = F/m ; k ox = 3.9 ; caps: C ox = ( k ox ε 0 ) t ox ; C j C j0 ( 1 + V R 0 ) M j = ; NMOS: β I ;(active) I D = 0.5β n ( V GS V tn ) n = µ n C ox ( W L) ; V tn > 0 ; V DS 0 ; (triode) D = β n (( V GS V tn )V DS ( V DS ) ) ; (triode) V DS ( V GS V tn ) ;(active) V DS ( V GS V tn ) ; V tn = V tn0 + γ( V SB + s s ) ; (( (subthreshold) I D I D0 e V GS V tn ) ( nv T )) V DS V T = ( 1 e ) ; PMOS: β I ;(active) I D = 0.5β p ( V GS V tp ) p = µ p C ox ( W L) ; V tp < 0 ; V DS 0 ; (triode) D = β p (( V GS V tp )V DS ( V DS ) ) ; (triode) V DS ( V GS V tp ) ;(active) V DS ( V GS V tp ) ; Simple cap model: C g = C ox WL ;if L min ; C gu C ox L min ; C g = C gu W ; C d = C s = C du W ; CMOS inverter: V TH = ( V DD + V tp + V tn r) ( 1 + r) ; r = ( µ n ( W L) n ) ( µ p ( W L) p ) ; RC delay est: t dr = t df = 1.τ ; τ = R eq C ; R eqn =.5 ( µ n C ox ( W L) n ( V DD V tn )) ; R eqp =.5 ( µ p C ox ( W L) p ( V DD + V tp )) ; ( W p W n ) opt = µ n µ p Unit delay est: t df t df1 = ( C L C L1 ) (( W L) n1 ( W L) n ) Min delay: t delay = τ inv ( C out C in ) ; total delay = Nfτ inv ; f N = C out C in ; usually f = 4 Power diss: P dyn = P 1 0 fc L V DD ; P dp = 0.5P 1 0 fv DD I peak ( t r + t f ); I peak = 0.5β n ( V TH V tn ) ; Elmore Delay: τ i C k R ik ; dist RC, τ RC ; k Interconnect: R = ( ρl) ( tw) ; R = ρ t ; C = ( ε ox wl) t ; C = ε ox lw ( h ( w h) ( t h) 0.5 ) ; Max delay constraint: T c t pcq + t pd + t setup Min Delay constraint:t hold t ccq + t cd Metastability: MTBF e T τ s = ( t rd F D F CLK ) SRAM: M3 is cell access transistor, M1 is inverter NMOS, M5 is inverter PMOS, SRAM read: W 1 W 3 ( V DD V A V tn ) ( ( ( V DD V tn )V A V A ) ) ; I cell = (( µ n C ox ) ) ( W 3 L) ( V DD V tn ) V BL = ( I cell t) C BL SRAM write: W 3 W 5 ( µ p ( V DD + V tp ) ) ( µ n (( V DD V tn )V A V A ) ) MOS Transistor; CMOS basic parameters. Channel length = 0.5µm, m j = 0.5, o = 0.9V V T0 ( V) γ ( V 0.5 ) µc ox ( µa V ) λ ( V 1 ) C ox ( ff µm ) C o ( ff µm) C j ( ff µm ) C jsw ( ff µm) NMOS PMOS V T0 is the threshold voltage with zero bulksource voltage; γ is used to account for nonzero bulksource voltage; µc ox is the transistor current gain parameter; λ is to account for the transistor finite output impedance (channel length modulation); is the gate capacitance per unit area; is the gate overlap capacitance per unit length; is the drain/source junction C o capacitance per unit area; C jsw is the drain/source junction capacitance per unit length to account for drain/source perimeter capacitance. Assume this value is the same for all perimeters C ox C j page 9 of 9
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