Digital Integrated Circuits 2nd Inverter


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1 Digital Integrated Circuits The Inverter
2 The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response Energy efficiency i Energy & power consumption
3 CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND
4 Two Inverters Share power and ground Abut cells V DD Connect in Metal
5 CMOS Inverter FirstOrder DC Analysis V DD V DD R p V OL = 0 VOH VDD V out V out V OH = V DD V M = f(r n, R p ) R n V in = V DD V in = 0
6 CMOS Inverter: Transient Response V DD V DD R p t phl = f(r on.c L ) phl on L = 0.69 R on C L V out V out C L C L R n Ex) V in = 0 V in = V DD (a) () Lowtohigh (b) Hightolow Rp or Rn ~ 수 KΩ C L ~ 수십 ff t phl =0.69RC ~ 수십ps
7 Voltage Transfer Characteristic ti
8 PMOS Load Lines I Dp V in =0 I Dn I Dn V in =0 V in =1.5 V in =1.5 V GSp =1 V DSp V DSp V out V GSp =2.5 V in = V DD +V GSp I Dn =  I Dp V out = V DD +V DSp Mirror around xaxis Shift over V DD
9 CMOS Inverter Load Characteristics I Dn V in = 0 V = 2.5 in PMOS V in = 0.5 V in = 2 NMOS V in = 1 V in = 1.5 V in = 1.5 V in = 1 V in = 2 V in = 1.5 V in = 1 V in = V in = 2.5 V in = 0 V out
10 CMOS Inverter VTC V out NMOS off PMOS res NMOS sat PMOS res 1.5 NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off V in
11 Switching Threshold as a function of Transistor Ratio V (V) M W p /W n
12 Switching Threshold
13 V out V OH Determining V IH and V IL g = inverter gain V M V in V OL V IL V IH A simplified approach
14 Inverter Gain gain V (V) in
15 Gain as a function of V DD V out (V V) 1 17% V out (V V) % V (V) in Gain= V (V) in
16 Impact of Process Variations 2.5 ut (V) V ou Good NMOS Bad PMOS Good PMOS Bd Bad NMOS Nominal V in (V)
17 Propagation Delay
18 CMOS Inverter Propagation Delay Approach 1 V DD t phl = C L V swing /2 I av I av V out C L ~ C L k n V DD V in = V DD
19 CMOS Inverter Propagation Delay Approach 2 V DD t phl = f(r on.c L ) = 0.69 R on C L V out C L V out ln(0.5) R on C L V DD V in = V DD R on C L t
20 Capacitance V DD V DD V in M2 C db2 M4 C g4 C gd12 V V V out V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L
21 CMOS Inverters V DD PMOS 1.2 μm =2λ In Out Metal1 Polysilicon NMOS GND
22 Transient Response? V (V V) out t plh t phl t p = 0.69 C L (R eqn +R eqp )/ t (sec) x 1010
23 Design for Performance Keep capacitances small Increase transistor sizes (W/L) watch out for selfloading! diffusion cap. Increase V DD (????) V DD Power but delay Sensitive to device variation (Ex. V T ) Signal swing sensitive to external noise
24 Delay as a function of V DD ) t (n normalized p V DD (V)
25 Device Sizing 38 x t p =0.69R eq (C int +C ext ) =0.69R eq C int (1+C ext /C int ) =t p0 (1+C ext /C int ) 3.2 t (sec c) p C int =S C iref t p =0.69(R ref /S)(S C iref )(1+C ex t/sc iref ) (for fixed load) Selfloading effect: Intrinsic capacitances dominate S
26 NMOS/PMOS ratio 5 x tplh tphl 4.5 t (se ec) p 4 tp β = W p /W n 3.5 Minimum i worst case delay for large cap. load β Minimum gate delay
27 Inverter Sizing
28 Inverter Chain In Out C L If C L is given:  How many stages are needed to minimize the delay?  How to size the inverters? May need some additional constraints.
29 Inverter Delay Minimum length devices, L=0.25μm Assume that for W P = 2W N =2W same pullup up and pulldown currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network 1 1 WP WN R P Runit Runit = RN = Wunit W = unit R W 2W W Delay (D): t phl = (ln 2) R N C L Load for the next stage: W Cgin = 3 W t plh = (ln 2) R P C L unit C unit
30 Inverter with Load Delay R W C L R W Load (C L ) k is a constant, equal to 0.69 Assumptions: no load > zero delay t p = kr W C L W unit = 1
31 Inverter with Load C P = 2C unit Delay 2W W C int C L C N = C unit Load Delay = kr W (C int + C L ) = kr W C int + kr W C L = kr W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load)
32 Delay Formula Delay ( C ) ~ R C W int + L t ( 1 + C / C ) = t ( 1 f / γ ) p = krw C int 1 L int p 0 + C int = γc gin with γ 1 f = C L /C gin effective fanout R = R unit /W ; C int =WC unit t p0 0 = 069R 0.69R unit C unit
33 Apply to Inverter Chain In Out 1 2 N C L t p = t p1 + t p2 + + t pn C gin, j+ 1 t + pj ~ RunitCunit 1 γcgin, j N N C gin j t p = t p j = t, + 1, p0 1 +, Cgin N =, + 1 j= 1 i= 1 γcgin, j C L
34 Optimal Tapering for Given N Delay equation has N  1 unknowns, C gin,2 C gin,n Minimize the delay, find N  1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j1 Size of each stage is the geometric mean of two neighbors C gin, j = Cgin, j 1C gin, j+ 1  each stage has the same effective fanout (C out /C in )  each stage has the same delay
35 Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: N f = F = C L / C Effective fanout of each stage: / gin,1 Minimum path delay p f = N F t = Nt + p0 ( 1 /γ ) N F
36 Example In C 1 1 f f 2 Out C L = 8 C 1 C L /C 1 has to be evenly distributed across N = 3 stages: f = 3 8 = 2
37 Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f t p = Nt t C f L p0 p = F C in = f N C in with N = ln ln ( ) p f F + = + 1/ N 0 γ / γ 1 = t p0 ln γ F ln F f t ln F γ ln f f 1 γ f = 0 ln 2 f For γ = 0, f = e, N = lnf f = exp ( 1+ γ f ) ln f
38 Optimum Effective Fanout f Optimum f for given process defined by γ f = exp 1+ ( γ f ) f opt = 3.6 for γ=1
39 Impact of SelfLoading on t p No SelfLoading, γ=0 With SelfLoading γ= u/ln(u) 40.0 x=10,000 x= x=100 x= u α=2.7 일반적으로 α=4
40 Buffer Design t ( 1 N /γ ) p = Nt p0 + F Buffer Design N f t p
41 Power Dissipation
42 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors
43 Dynamic Power Dissipation Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C * 2 L V dd * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. Vout 0 1 되는주기
44 Modification for Circuits with Reduced Swing V dd V dd V dd V t C L E 0 1 = C L V dd ( V dd V t ) Can exploit reduced swing to lower power (e.g., reduced bitline swing in memory)
45 Transistor Sizing for Minimum Energy In Out C g1 1 f C ext Goal: Minimize Energy of whole circuit Design parameters: f and V DD tp tpref of circuit with f=1 and V DD =V ref t t p p0 f F = t p γ f γ VDD V V DD TE
46 Transistor Sizing (2) Transistor Sizing (2) Transistor Sizing (2) Transistor Sizing (2) Performance Constraint (γ=1) (γ ) f F f V V V f F f t t TE f ( ) ( ) = + = + = F f V V V V V V F f t t t t TE DD TE ref ref DD ref p p pref p Energy for single Transition ( )( ) [ ] = F f V E F f C V E g DD γ = F F f V V E E ref DD ref 4 2 2
47 Transistor Sizing (3) V DD =f(f) E/E ref =f(f) vdd (V) F= norma alized energy f f
48 Short Circuit Currents Vd d Vin Vout C L 0.15 I VDD (ma) V in (V)
49 How to keep ShortCircuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can t do this for cascade logic, so...
50 Minimizing ShortCircuit Power Vdd =3.3 P norm 4 3 Vdd = Vdd = t sin /t sout
51 Leakage Vdd Vout Drain Junction Leakage SubThreshold Current Subthreshold current one of most compelling issues in lowenergy circuit design!
52 ReverseBiased Diode Leakage GATE p + p+ N p +  V dd Reverse Leakage Current I DL = J S A J S = pa/μm 2 at 25 deg C for 0.25μm CMOS J S doubles for every 9 deg C!
53 Subthreshold Leakage age Component
54 Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Wasted energy Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)
55 Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question ( V by 2010!) Reduce switching activity Reduce physical capacitance Device Sizing: for F=20 f opt (energy)=3.53, f opt (performance)=4.47
56 Impact of Technology Scaling
57 Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced But also want to be faster, smaller, lower power
58 Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 23 years
59 Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Year of Introduction Technology node [nm] Supply [V] Wiring levels Max frequency [GHz],LocalGlobal Max μp power [W] Bat. power [W] Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
60 ITRS Technology Roadmap Acceleration Continues
61 Technology Scaling (1) 10 2 Minim mum Featur re Size (mic cron) Year Minimum Feature Size
62 Technology Scaling (2) Number of components per chip
63 Technology Scaling (3) t p decreases by 13%/year 50% every 5 years! Propagation Delay
64 Technology Scaling (4) 100 x1.4 / 3 years 1000 κ 0.7 Po ower Dissip pation (W W) Year x4 / 3 years (a) Power dissipation vs. year. MPU DSP 95 Powe r Density (mw/mm 2 ) κ Scaling Factor κ (normalized by 4μm design rule) (b) Power density vs. scaling factor. 10 From Kuroda
65 Technology Scaling Models Full Scaling (Constant Electrical Field) ideal model dimensions and voltage scale together by the same factor S Fixed Voltage Scaling most common model until recently only dimensions scale, voltages remain constant General Scaling most realistic for todays situation voltages and dimensions scale with different factors
66 Scaling Relationships for Long Channel Devices
67 Transistor Scaling (velocitysaturated devices)
68 μprocessor Scaling P.Gelsinger: μprocessors for the New Millenium, ISSCC 2001
69 μprocessor Power P.Gelsinger: μprocessors for the New Millenium, ISSCC 2001
70 μprocessor Performance P.Gelsinger: μprocessors for the New Millenium, ISSCC 2001
71 2010 Outlook Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 active Power P.Gelsinger: μprocessors for the New Millenium, ISSCC 2001
72 Some interesting questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation
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