# Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman

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1 Digital Microelectronic Circuits ( ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1

2 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor» Shockley Model» Channel Length Modulation, Velocity Saturation, Body Effect

3 This Week - Motivation The Inverter, or NOT gate, is truly the nucleus of all digital designs. We will analyze the inverter and find its characterizing parameters. Once its operation and properties are clearly understood, designing and analyzing more intricate structures, such as NAND gates, adders, multipliers and microprocessors is greatly simplified. This lecture focuses on the static CMOS inverter the most popular at present and the basis for the CMOS digital logic family. In In Out Out 3

4 What will we learn today? 4.1 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4..1 The Inverter s VTC 4.. Operating Regions 4..3 Switching Threshold 4..4 Noise Margins Parasitic Capacitances 4.3. Propagation Delay Device Sizing - β Device Sizing S Sizing a Chain of Inverters Dynamic Power 4.4. Short Circuit Power Static Power Total Power Consumption 4.5 Summary 4

5 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary As usual, we ll start with AN INTUITIVE EXPLANATION 5

6 An Intuitive Explanation A Static CMOS Inverter is modeled on the double switch model. The basic assumption is that the switches are Complementary, i.e. when one is on, the other is off. When the top switch is on, the supply voltage propagates to the output node. When the bottom switch is on, the ground voltage is propagated out. V + - V0 6

7 An Intuitive Explanation Now we will replace the model switches with real voltage controlled switches MOS Transistors. We will use complementary transistors one nmos and one pmos, and hook them up to the same input voltage. Now, when we set a high input voltage, the nmos is on and the pmos off. The ground voltage propagates. When we put a low input voltage, the pmos is on and the nmos is off. The supply voltage propagates. We ve built an inverter! V V in =V =0 + - V out =0 V out =V in 7

8 An Intuitive Explanation The voltage connected to the Source of the pmos is known as the Supply Voltage or V DD.* We mark the connection to V DD with a horizontal or slanted bar. Accordingly, V DD represents a logical 1 and GND represents a logical 0. Inputting V DD to the CMOS inverter will present GND at the output. Inputting GND will present V DD at the output. This characteristic is non-trivial and is one of the advantages of CMOS design. It is known as Rail to Rail Swing.** * It can also be called V CC, regarding the Collector of BJT transistors. ** Rails are the supply voltages, i.e. V DD and GND. If a voltage is connected to the nmos Source instead of GND, we refer to this voltage as V SS. 8

9 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary Now that we understand the principles, we ll analyze STATIC OPERATION 9

10 Reminder: The Unified MOSFET Model W V n DSeff I k V V V 1 V Ln V min V V, V, V DSn n GSn Tn DSeff n DSn DSeff GSn Tn DSn DSATn 10

11 Reminder: Static Properties VTC Noise Margins 11

12 The Inverter s VTC To construct the VTC of the CMOS inverter, we need to graphically superimpose the I-V curves of the nmos and pmos onto a common coordinate set. We can see that: I V V SDp GSn DSn I DSn V V V Vin SGp DD in V V V Vout SDp DD out V in V SGp V GSn V SDp I SDp V DD V out I V DSn DSn 1

13 The Inverter s VTC Since V in and V out are the input and output voltages of the nmos transistor, we will change the coordinates of the pmos. I SDp DSn V V V out DD SDp V V V I in DD SGp DSn I SDp V in =0 V in =1.5 V SGp =.5 V SGp =1 V out SDp For V DD =.5V 13

14 The Inverter s VTC The Now, intersection we will superimpose of corresponding the modified load pmos lines shows I-V curves the DC on operating the nmos points, I-V graphs: where the currents of the nmos and pmos are equal. I DSn V in =0 V in =V DD V in =V DD / V in =V DD / V in =V DD V in =0 V out 14

15 The Inverter s VTC Putting all the intersection points on a graph with the corresponding output voltage will give us the CMOS inverter s VTC: V out V DD V DD / V DD / V DD V in 15

16 Intuitive Operating Regions V out V DD V DD / V DD / V DD V in 16

17 Operating Regions Let s figure out what region of operation each transistor is in throughout the VTC curve.* * Considering Long Channel Transistors With V T <V DD / V DD Vout V out V in V VGSn Vin VT Cutoff T V SGp V SDp V DD / VSGp VDD Vin VT VSDp VDD Vout VSGp VT Linear V GSn V T V DD / V DD V in 17

18 Operating Regions So now, let s jump to the other side of the VTC. V out V V V in DD T V DD VSGp VDD Vin VT Cutoff V SGp V DD / VGSn Vin VDD VT VT VDSn Vout VGSn VT Linear V DSn V GSn V out V DD / V DD -V T V DD V in 18

19 Operating Regions Now, back to the VTC regions. Let s see what happens when we raise the input voltage slightly past V T. V DD Vout V out V in V T V SGp V SDp VGSn Vin VT VDSn Vout VDD VGSn VT Sat VSGp VDD Vin VT VSDp VDD Vout 0 VSGp VT Linear V GSn V T +ΔV V DD V in 19

20 Operating Regions The same when V in is a bit more than V T lower than V DD. V out V V V V in DD T V DD V SGp V SDp VSGp VDD Vin VT VSDp VDD Vout VDD VSGp VT Sat VGSn Vin VT VDSn Vout 0 VGSn VT Linear V GSn V out V DD -V T -ΔV V DD V in 0

21 Operating Regions Finally, we have the middle area, where: V out V DD V V V in DD VSGp VDD Vin VDD VT Sat VSDp VDD Vout VDD VSGp VT V SGp V SDp VGSn Vin VDD VT VDSn Vout VDD VGSn VT V out Sat V GSn V DD / V DD V in 1

22 Operating Regions To Sum it up: V DD V out nmos off pmos - res nmos sat pmos - res nmos sat pmos - sat nmos res pmos - sat Towards the rails, one of the transistors is cut off, and the other is resistive. Once the cut off transistor starts conducting, it immediately is saturated. As we approach the middle input voltages, both transistors are saturated. The VTC slope is known as the Gain of the gate. nmos res pmos - off V DD V in

23 Switching Threshold The Switching Threshold, V M, is the point where V in =V out. This can be calculated:» Graphically, at the intersection of the VTC with V in =V out V out V DD V M» Or analytically, by equating the nmos and pmos saturation currents with V in =V out. V DD V in 3

24 Switching Threshold But let s start with the intuitive approach 4

25 Switching Threshold Let s analytically compute V M.» Remember, the saturation current for a MOSFET is given by:» Lets assume λ=0 and we ll equate the two currents:» Now we ll substitute: I k V V V 1 DS GS T DS k k n I V V V V p D GSn Tn SGp Tp VGSn Vin V V M SGp VDD Vin VDD VM» And we ll arrive at: V M V r V V 1 r Tn DD Tp r k k p n 5

26 Switching Threshold As we can see, r is an important factor in setting the switching threshold. r is a design parameter, that is set by the drive strength ratios of the nmos and pmos: r long _ channel k k p n W k k C L ox W L Using the current equations again, we can find the drive strength ratio for a desired V M : k p VM VTn k V V V n DD M Tp 6

27 Switching Threshold A symmetric VTC (V M =V DD /) is often desired. In this case: V M V V r V V DD 1 r Tn DD Tp W n W L L Generally, the same length (L min ) is taken for all transistors in digital circuits, and so for a symmetric VTC: p p n W W p n n p...4 7

28 Reminder: Noise Margins V OHmax V OHmin V DD NM V V H OH min IH NM H V IH V OLmax NM L V IL V OLmin GND NM V V L IL OL max NM min NM, NM L H 8

29 Noise Margins One of the CMOS logic family s advantages is a Full Rail to Rail Swing. In other words: V V OH max OLmin To calculate the Noise Margins, we will need to find V IL and V IH. These are the points where the gain is -1. V V out DD GND To do this we will equate the currents:» V IL nmos sat, pmos res» V IH nmos res, pmos sat V DD V DD V in 9

30 Noise Margins Let s calculate V IH : V k I res k V V V I sat V V Assuming matching devices (k n =k p, V Tn =V Tp ): Differentiating and equating -1, we reach: DSn p DSn n GSn Tn DSn DSp GSp Tp V 1 out V V V V V V IN T out DD IN T 1 V 5 V V 8 IH DD T Doing the same for V IL or using symmetry, we reach: 1 V 3 V V 8 IL DD T Accordingly, for a matched long-channel device, and assuming V OHmin V OHmax and V OLmax V OLmin in CMOS, we get: 1 NM NM V V V 0 3V V H L DD IH IL DD T Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 8 4: The CMOS Inverter 30

31 Noise Margins The previous analysis assumed many things and therefore SHOULD NOT be memorized. Let us look at the noise margins intuitively to try and understand trade offs: 31

32 Summary of Static Properties When Vin<VT or Vin>VDD-VT, one of the networks (PUN/PDN) is off, providing Rail to Rail Swing. The skew of the VTC is set by the sizing ratio between the PUN and PDN. Analytic Noise Margin calculation is rigorous and approximation should be used when possible. 3

33 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary Now that we see how the inverter behaves in steady state, we will analyze it s transient: DYNAMIC OPERATION 33

34 Reminder: Dynamic Properties Propagation Delay Rise/Fall Time 34

35 Parasitic Capacitances Remember that our transistors have capacitance connected to the output node. We ll calculate the capacitance values in the next lecture, but for now, let s just use and equivalent output capacitance. When the input is low our pmos is a non-linear resistor and our nmos is cut off, so we get a simple RC circuit. Our capacitance is charged, bringing the output voltage to V DD. V + - V DD C eq 35

36 Parasitic Capacitances When the input is high, we essentially have closed the top switch and opened the bottom one. This creates a resistive path from the capacitor to GND, and blocks the path from the supply to the output. Again we have an RC network, though this time we are just discharging the capacitance to GND. We end up with an output equal to GND. 0 C eq 36

37 Parasitic Capacitances So we saw that, a switching CMOS inverter charges and discharges a parasitic output capacitance. During the switching process, we can create a model that will transform the circuit into a simple RC network. In this way, we can easily derive a first order analysis of the CMOS dynamic operation for propagation delay and power consumption calculation. 37

38 Parasitic Capacitances For now, let us make the following assumptions:» A transistor has a gate capacitance that is proportional to its area (W*L)» A transistor has a diffusion capacitance that is proportional to its width (W) 38

39 Parasitic Capacitances For now we will use a very simple model to represent all the parasitic capacitances between the output node and ground. Driver C C C N C load out wire in Load C wire C out,1 C in, C int C ext 39

40 Propagation Delay Using our simple model for load capacitance, we can write: Assuming an ideal step at the input, the propagation delay, t pd is the time it takes the output to (dis)charge 50% of its voltage. We will look at three ways to calculate the propagation delay:» By solving the integral above.» By approximating the average current» By using equivalent resistance t t dt v v 1 1 C load i v v out out dv out 40

41 t pd solving the integral We ll start with V in =0. Accordingly, P1 is open and N1 is closed, causing the output voltage to be held at V out =V DD At t=0, V in changes from 0 to V DD, closing P1 and opening N1. This causes the output to discharge like a first order RC network. V in V DD V out t=0 t C eq V DD t 41

42 t pd solving the integral At this point V DSn =V DD >V GS -V T, so N1 is in saturation and the discharge current is given by: n I k V V V 1 DSn In T out V DD V DD -V T Assuming λ=0 and integrating until N1 enters the linear region: V out DD T C C V V V load t p1 dv VDD i kn D sat VDD VT V V DD DD T V DD / t p1 t phl t 4

43 t pd solving the integral Now V DSn <V GS -V T and so N1 goes into linear operation with: V I DSn res kn Vin VT Vout We ll write an expression for the change in voltage: out V DD V DD -V T V DD / And arrive at the following integral: V out t p dv i dt k V V V V t phl DSn n out out in T out Cload Cload dt Cload k V V V DD t1 VDD V n DD T T V dvout 1 V V DD T out V out t p1 t p t phl t 43

44 Using the equality: We get: t p dx 1 ln1 ax x ax t pd solving the integral C load 3VDD 4V T ln kn VDD And putting together the two parts, we get: For V T =0.V DD, we get: V DD V DD -V T V DD / V out C load V 1 T 3V 4 1 ln DD V T t phl t p t p kn VDD VT VDD VT VDD t t p t p1 t phl phl 1.6C load kv n DD t p Cload k V V n DD T V V DD DD V TH V DD dvout 1 V V T out V out t 44

45 t pd average currents Instead of solving the integral, we can sometimes assume a linear change in current to make life much easier. This assumption just lets us find the average current between t=0 and t=t phl and calculate: t phl C i load V DSn avg 1 C load V DD 0 i i t DSn DSn phl 45

46 Example t pd average current» Step input into a CMOS inverter with a minimum sized nmos driving a 1.5fF load. t 0» VDS=VDD, VGS-VT=VDD-VT t pd min,, V V V V V V DSeff DD DD Tn DSatn DSat I DS t0 k n VGTnVDSatn 0.5V DSatn 1 VDSn A 0.18» VDS=VDD/, VGS-VT=VDD-VT min,, V V V V V V DSeff DD DD Tn DSatn DSat I DS t0 kn VGTnVDSatn VDSatn VDSn A

47 t pd average current» The average current is: I Avg 0.5 I DS t0 I DS t pd 8.65 A» So we can find the delay: V t V t0 pd 0.9 t pd CL 1.5 f 16.33ps I 8.65 Avg 47

48 t pd equivalent resistance A good way to estimate the propagation delay is by finding the resistance of the MOSFET during the transition and using this resistance in quick calculations. The primary approach to deriving such an equivalent resistance is to calculate the transistor s average resistance throughout its operation (ON) period. t t 1 1 VDS t Req averaget t 1... t R on t Ron t dt dt t t t t I t 1 t 1 t DS R on t R t 1 on 48

49 t pd equivalent resistance Now, we will calculate the propagation delay of a short channel inverter, by using the equivalent resistance to discharge a capacitor from V DD to V DD /. Assuming V DD >>V DSATn, we can assume that throughout the propagation delay, the transistor is velocity saturated. We can write: VDD 1 VDS 3 VDD 7 eq DS 1 DD V / DD I / DSAT 1 VDS 4 I DSAT 9 V R dv V DD V I DSAT kn VDD VT VDSAT DSAT 49

50 t pd equivalent resistance For example, if VDD=1.8V: I DSATn k n VGTnVDSatn 0.5V DSatn A VDD 7 Reqn 1 VDD 4 I 9 DSAT k A 9 50

51 t pd equivalent resistance So all we need is to use our magic equation: t 0.69R C k 1.5 f 16.75ps pdhl eqn L Remember that for t pd, we also need R eqp for: t pd t plh t 0.69C R R phl load eqp eqn 51

52 t pd equivalent resistance To calculate and analyze the parameters that affect the propagation delay, we will take λ=0 and get: t phl 3 V V C 0.69Cload I DSATn k V V V Accordingly, we can minimize the delay in the following ways:» Minimize C load.» Increase W/L» Increase V DD DD DD load n DSATn DD Tn V DSAT 5

53 Last Lecture CMOS Inverter» Intuitive Explanation» VTC» VM» Noise Margins» Propagation Delay 53

54 Affect of Device Sizing So we saw that to reduce the propagation delay, we need to increase the device sizes (W/L). But how much should we increase them? What are the tradeoffs? For this, we will discuss two sizing parameters:» Beta Ratio (β)» Upsizing Factor (S) 54

55 What happens when we upsize a transistor? Effective resistance decreases: Gate and Drain Capacitance increase: 55

56 Device Sizing - β Device Sizing is the Width to Length ratio (W/L) of the transistor. When discussing a CMOS logic gate, we relate to the pmos/nmos ratio ((W p /L p )/(W n /L n )).» We will call this ratio β. To get a balanced inverter (i.e. V m =V DD /) we usually will need β=3-3.5, mainly due to the mobility ratio of holes and electrons. This generally equates the propagation delay of High-to-Low and Low-to-High transitions. However, this does not imply that this ratio yields the minimum overall propagation delay. 56

57 Device Sizing - β How can this be?» To get a faster t plh, we need to enlarge the pmos width.» This increases the parasitic capacitance (C load ), degrading t phl. 57

58 Device Sizing - β 58

59 Device Sizing - β We will now find the optimum ratio for sizing an inverter, considering two identical cascaded CMOS inverters. The load capacitance of the driving gate is: C C C C load out1 in wire Assuming the input capacitance is the gate capacitance of the transistors (C g ) and the output capacitance is the drain capacitance (C d ), we can write: Driver C C C C C C C out,1 load dp1 dn1 gp gn wire C int C ext Load C wire C in, Assuming a linear dependence on device size, we get: 1 1 W L W L C C C C load dn gn wire p n 59

60 Device Sizing - β Noting that we have reduced the equivalent resistance of the pmos by β, we can write the first order RC propagation delay: 0.69C Reqp load t pd Reqn Reqp Cdn1 Cgn C wire Reqn Now we just need to find the minimum: dt pd 0 d R eqp C R wire opt 1 R C 1 C R Cdn1Cgn Cwire eqn dn gn eqn A typical optimum for β is usually around. eqp 60

61 Conclusions: Device Sizing - β» A balanced inverter isn t usually the fastest possible inverter.» A typical optimal pmos/nmos ratio for performance is given by: Reqp opt R eqn 61

62 Device Sizing - S We saw how the ratio between the pmos and nmos can be optimized to improve performance. Now, we will take a balanced inverter and see how upsizing affects the intrinsic or unloaded delay. We will start by writing the delay as a function of the intrinsic capacitance (diffusion and overlap) and the extrinsic capacitances (fanout and wiring): C C C load int ext t 0.69R C 0.69R C C pd eq load eq int ext 6

63 Device Sizing - S Now, we will mark the minimal intrinsic delay as t p0. This is the delay of a minimum sized balanced inverter only loaded by its own intrinsic capacitance (C ext =0): tp0 0.69Rref Cref We will now mark the sizing factor, S. This is the relative upsizing of the inverter, i.e. C int =SC ref and accordingly R eq =R ref /S. Now we can write the delay of an upsized inverter: R t 0.69R C C 0.69 SC C S ref int pd eq ext ref ext C ext C ext 0.69Rref Ciref 1 t p0 1 SC ref SC ref 63

64 Device Sizing - S t t C pd p0 1 ext SC ref 64

65 Conclusions: Device Sizing - S t t C pd p0 1 ext SC ref» The intrinsic delay of an inverter (t p0 ) is independent of the sizing of the gate and is purely determined by technology. When no load is present, an increase in the drive of the gate is totally offset by the increased capacitance.» To minimize a loaded inverter s delay, S should be enlarged, but at the expense of a substantial gain in area. 65

66 Summary of Dynamic Parameters We can calculate t pd in several ways, but the easiest is to measure the equivalent resistance during a typical transition. One of our main techniques to improve the delay is through transistor sizing, which we discussed in two fashions:» Setting the optimal ratio between the PUN/PDN.» Upsizing the gate to deal with a large output load. 66

67 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary And now that we fully understand the static and dynamic operation of the CMOS Inverter, it s time to take a look at POWER CONSUMPTION 67

68 Dynamic Power Assuming an ideal step input, we can analyze the energy consumed from the supply of the equivalent circuit during a Low-to-High transition is given by: dv E i t V dt V C dt C V dv C V dt VDD out VDD 0 VDD DD DD 0 load load DD 0 out load DD Now, looking at the energy stored in the load capacitance, we get: dv C V E i t V dt C V dt C V dv VDD out load DD Charge 0 VDD out 0 load out load 0 out out dt 68

69 Dynamic Power E C V V load DD DD E Charge C load V DD Analyzing these results, we see that the energy required to charge the output capacitance is twice the energy stored on the capacitor at the end of the transition. This is relatively surprising and very important. It means that half of the energy was wasted on the pmos resistance independent of its size! 69

70 Dynamic Power Assuming the input changes now from zero to one, we now get a High-to-Low transition. Here, the supply is disconnected, and the charge stored on the capacitance flows through the nmos to the ground. The energy dissipated is the total energy stored on the output capacitance, as no charge is left: dv C V E i t V dt C V dt C V dv 0 out load DD discharge 0 DSn out 0 load out load V out out dt DD The sum of the charge and discharge energy is obviously equal to the energy supplied: E E E C V charge discharge V load DD DD 70

71 Dynamic Power Conclusions:» Each charge and discharge cycle dissipates a fixed amount of energy, independent of the size of the device.» The effective energy is the charge stored on the capacitance. The rest of the energy is wasted as heat burned on the pmos (charge) and nmos (discharge) resistance. To compute the Power Dissipation, we calculate the total energy wasted per one second. For a circuit that completes a Low-to-High transition f 01 times per second (and therefore a High-to-Low transition as well ), the dynamic power consumption is: Pdyn CloadV DD f0 1 71

72 Dynamic Power We said that the Power Dissipation is a factor of the switching frequency of the gate. But the gate only switches when its input changes. In other words, the switching activity is smaller than the circuit frequency. We can rewrite the Dynamic Power expression using the activity factor, α of the inverter, expressing the probability of the output to switch: P C V f C V f dyn load DD eff DD C eff is the effective capacitance of a complex circuit, describing the average capacitance that actually switches each cycle. 7

73 Short Circuit Power During the above analysis, the input was an ideal step function, immediately closing one transistor when the other was opened. In a real circuit, the input signal has a non-zero rise/fall time, resulting in a time interval with both the pmos and nmos transistors open. This provides a direct path from V DD to GND, with a current known as Short Circuit current. This is shown in the following waveforms: 73

74 Short Circuit Power The energy dissipated via short circuit power is the area under the triangles: I peaktsc I peaktsc E V V t V I sc DD DD sc DD peak And the average power consumption is: Psc tscvdd I peak f 74

75 Short Circuit Power The short circuit interval, t sc, is the margin between the threshold voltages of the transistors. Assuming a linear input transition: t sc V DD V V DD T t rise( fall)

76 Short Circuit Power What affects the short circuit power?» A short input rise time with a large output capacitance (large fall time) minimizes short circuit power, as the peak current is very small. 76

77 Short Circuit Power What affects the short circuit power?» small output capacitance relative to the input rise time causes extensive short circuit power, as the peak current is maximal (saturation current of the transistors). Conclusion:» Try to keep the input and output rise/fall times similar to maximize performance and minimize short circuit power. 77

78 Static Power Ideally, a MOSFET transistor is a perfect switch. In such a case, a CMOS inverter never has a conducting path in steady state, resulting in no static power dissipation. However, in reality, MOSFET transistors never completely turn off. 78

79 Static Power Since static power is constantly consumed, the power dissipation can be simply expressed as: Pstatic IstaticVDD Sources of static power are beyond the scope of this course, however they are quickly becoming the dominant source of power in advanced sub-micron technologies. For further probing, see these subjects:» Subthreshold current» Hot Electrons» DIBL» Punchthrough 79

80 Total Power Consumption As we saw above, there are three components to the power dissipation of a CMOS inverter:» Dynamic Power» Short Circuit Power» Static Power Putting them all together, we get the total power consumption of a CMOS logic gate: P P P P fc V fv I t V I total dyn sc static load DD DD peak sc DD static 80

81 Total Power Consumption We previously learned that the power-delay-product (PDP) measures the average energy of a switching event: 1 PDP P t C V f t C V dyn pd load DD max pd load DD Since both Power and PDP give a clear advantage to energy reduction versus performance, we measure the energy-delay-product (EDP) as a combined measurement of the two: 1 EDP PDP t C V t pd load DD pd 81

82 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary Okay, enough with the inverter. But before we go on, let s go over a short SUMMARY 8

83 Summary The CMOS inverter is characterized by:» A pmos Pull-Up device and an nmos pull down device.» The pmos is usually wider due to inferior current driving.» An almost ideal VTC with a full rail to rail swing.» Noise margins of a balanced inverter are close to V DD /» The steady state response is not affected by fanout. Propagation delay:» Can be approximated as:» Small loads make faster drivers.» Widening the transistors improves the delay. Power Dissipation:» Dominated by dynamic power, given by: Reqp Reqn 0.69Cload» Short circuit power can be reduced by equating input/output slopes.» Static Power is a problem out of the scope of this course. t pd Pdyn fcloadv DD 83

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