COMP 103. Lecture 16. Dynamic Logic

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1 COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03 L6 Dynamic CMOS. Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of N requires 2N devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires only N + 2 transistors To realize logic functions, it takes a sequence of two phases: - Precharge, and - conditional evaluation COMP03 L6 Dynamic CMOS.2

2 Dynamic Gate In In 2 In 3 PDN C L C Two phase operation Precharge ( = 0) Evaluate ( = ) COMP03 L6 Dynamic CMOS.3 Dynamic Gate off on!((&) C) In In 2 In 3 PDN C L off on C Two phase operation Precharge ( = 0) Evaluate ( = ) COMP03 L6 Dynamic CMOS.4

3 Conditions on put Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. It is always a high-to-low transition put can be in the high impedance state during and after evaluation (PDN off), state is stored on C L COMP03 L6 Dynamic CMOS.5 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) should be smaller in area than static complementary CMOS Full swing outputs (V OL = GND and V OH = V DD ) Nonratioed - sizing of the devices is not important for proper functioning (only for performance) Faster switching speeds reduced load capacitance due to lower number of transistors per gate (C int ) so a reduced logical effort reduced load capacitance due to smaller fan-out (C ext ) no I sc, so all the current provided by PDN goes into discharging C L Ignoring the influence of precharge time on the switching speed of the gate, t plh = 0 but the presence of the evaluation transistor slows down the t phl COMP03 L6 Dynamic CMOS.6

4 Properties of Dynamic Gates, con t Power dissipation should be better consumes only dynamic power no short circuit power consumption since the pull-up path is not on when evaluating lower C L - both C int (since there are fewer transistors connected to the drain output) and C ext (since there the output load is one per connected gate, not two) by construction can have at most one transition per cycle no glitching ut power dissipation can be significantly higher due to higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so set V M, V IH and V IL all equal to V Tn low noise margin (NM L ) Needs a precharge clock COMP03 L6 Dynamic CMOS.7 Dynamic ehavior 2.5 In In 2 Voltage Evaluate.5 In 3 In In & Time, ns Precharge #Trns V OH V OL V M NM H NM L t phl t plh t p 6 2.5V 0V V Tn 2.5-V Tn V Tn 0ps 0ns 83ps COMP03 L6 Dynamic CMOS.8

5 Gate Parameters are Time Independent The amount by which the output voltage drops is a strong function of the input voltage and the available evaluation time. Noise needed to corrupt the signal has to be larger if the evaluation time is short i.e., the switching threshold is truly time independent. Voltage (V) V out (V G =0.45) V out (V G =0.55) Vout (V G =0.5) V G -0.5 COMP03 L6 Dynamic CMOS Time (ns) Power Consumption of Dynamic Gate In In 2 In 3 PDN C L Power only dissipated when previous = 0 COMP03 L6 Dynamic CMOS.0

6 Dynamic Power Consumption is Data Dependent Dynamic 2-input NOR Gate ssume signal probabilities P = = /2 P = = /2 Then transition probability P 0 = P out=0 x P out= = 3/4 x = 3/4 Switching activity can be higher in dynamic gates! P 0 = P out=0 COMP03 L6 Dynamic CMOS. Issues in Dynamic Design : Charge Leakage = C L V Evaluate Precharge Leakage sources Minimum clock rate of a few khz COMP03 L6 Dynamic CMOS.2

7 Impact of Charge Leakage put settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage. 2.5 Voltage (V) COMP03 L6 Dynamic CMOS Time (ms) Solution to Charge Leakage Keeper compensates for the charge lost due to the pulldown leakage paths. Keeper M kp C L! Same approach as level restorer for pass transistor logic COMP03 L6 Dynamic CMOS.4

8 Issues in Dynamic Design 2: Charge Sharing =0 C a C b C L Charge stored originally on C L is redistributed (shared) over C L and C leading to static power consumption by downstream gates and possible circuit malfunction. When V out = - V DD (C a / (C a + C L )) the drop in V out is large enough to be below the switching threshold of the gate it drives causing a malfunction. COMP03 L6 Dynamic CMOS.5 Solution to Charge Redistribution M kp Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) COMP03 L6 Dynamic CMOS.6

9 Issues in Dynamic Design 3: ackgate Coupling Susceptible to crosstalk due to ) high impedance of the output node and 2) capacitive coupling 2 capacitively couples with through the gate-source and gate-drain capacitances of M4 =0 M C L = M 6 M 4 M 5 2 =0 C L2 =0 M 2 M 3 In Dynamic NND Static NND COMP03 L6 Dynamic CMOS.7 ackgate Coupling Effect Capacitive coupling means drops significantly so 2 doesn t go all the way to ground 3 Voltage 2 0 In Time, ns 4 6 COMP03 L6 Dynamic CMOS.8

10 Issues in Dynamic Design 4: Clock Feedthrough special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node C L Coupling between and input of the precharge device due to the gatedrain capacitance. So voltage of can rise above V DD. The fast rising (and falling edges) of the clock couple to. COMP03 L6 Dynamic CMOS.9 Clock Feedthrough In 2.5 Clock feedthrough In 2.5 In 3 In 4 Voltage In & Time, ns Clock feedthrough COMP03 L6 Dynamic CMOS.20

11 Cascading Dynamic Gates V In 2 In 2 V Tn V t Only a single 0 transition allowed at the inputs during the evaluation period! COMP03 L6 Dynamic CMOS.2 Domino Logic In In 2 0 PDN In 4 M kp PDN 2 In 3 In 5 COMP03 L6 Dynamic CMOS.22

12 Why Domino? In In i In j PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! COMP03 L6 Dynamic CMOS.23 Domino Manchester Carry Chain P 0 P P 2 P 3 C i,0 G 0 G G 2 G 3 C i,4 COMP03 L6 Dynamic CMOS.24

13 Domino Manchester Carry Chain P 0 P P 2 P 3 4 C i,0 5 G C i,4 G 3 G 2 2 G !(G 0 + P 0 C i,0 )!(G + P G 0 + P P 0 C i,0 ) COMP03 L6 Dynamic CMOS.25 Properties of Domino Logic Only non-inverting logic can be implemented, fixes include can reorganize the logic using oolean transformations use differential logic (dual rail) use np-cmos (zipper) Very high speed t phl = 0 static inverter can be optimized to match fan-out (separation of fan-in and fan-out capacitances) COMP03 L6 Dynamic CMOS.26

14 Variation #: Differential (Dual Rail) Domino = off on M kp M kp 0 0!!! =!() Due to its high-performance, differential domino is very popular and is used in several commercial microprocessors! COMP03 L6 Dynamic CMOS.27 Variation #2: np-cmos (Zipper) In In 2 In 3 PDN 0! In 4 In 5! PUN (to PDN) to other PDN s to other PUN s Only 0 transitions allowed at inputs of PDN Only 0 transitions allowed at inputs of PUN COMP03 L6 Dynamic CMOS.28

15 DCVS Logic 0 on off off on 0! In!In In 2!In 2 PDN off on PDN2 on off PDN and PDN2 are mutually exclusive COMP03 L6 Dynamic CMOS.29 DCVSL Example!!!! COMP03 L6 Dynamic CMOS.30

16 How to Choose a Logic Style Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing 4-input NND Style # Trans Ease Ratioed? Delay Power Comp Static CPL* domino DCVSL* no no no yes clk 4 * Dual Rail Current trend is towards an increased use of complementary static CMOS: design support through D tools, robust, more amenable to voltage scaling. COMP03 L6 Dynamic CMOS.3 Example Consider the circuit shown in the Figure & implemented in Domino Logic. nswer the following questions: Vdd What logical function does this circuit implement? When does the circuit precharge and evaluate? Can the output F be the input to a duplicate circuit using F as input? φ F Justify your answer. This next part is concerned with the analysis of the charge sharing problem. Use the following parameters to calculate the final voltage at node F during the evaluate cycle: Supply Voltage = 2.5V, C, D = 0 at all times; F is precharged to Vdd. During evaluate cycle, switches from low to high. φ X C D ll transistors are the same size. VT = 0.5V Neglect body effect. Csb = Cdb = 3fF; Ignore all other caps. lso assume that F has a 30fF load attached to it. COMP03 L6 Dynamic CMOS.32

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