Lecture 7: Logic design. Combinational logic circuits
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1 /24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic computing Digital with more than two states is not practical Combinational : depends only on the current s (no memory of past s) combinational Seuential : depends on the current s as well as (some) previous s Inf2C (Computer Systems) Combinational circuits Inverter (or NOT gate): and invert the signal IN AND gate: minimum 2 s and only if both s are = IN IN IN 2 IN IN 2 = IN IN 2 Inf2C (Computer Systems)
2 /24/28 Combinational circuits OR gate: if at least one is IN IN 2 NAND gate: IN IN 2 if both s are not (NOT AND) = IN + IN 2 IN IN 2 IN IN 2 = IN IN 2 Inf2C (Computer Systems) Combinational circuits NOR gate: if no is (NOT OR) IN IN 2 Multiple- gates: AND IN IN 2 2 = IN + IN 2 OR IN IN n = if all IN i = IN IN n = if any IN i = Inf2C (Computer Systems)
3 /24/28 Multiplexer Multiplexer: a circuit for selecting one of many s i i z=, if c= z i, if c= i c i i c z z = i i c + i i c + i i c + i i c = i i c + i i c + i i c + i i c = (i + i )i c + i (i + i )c = i c + i c sum of products form Inf2C (Computer Systems) A multiplexer implementation Sum of products form: i c + i c Can be implemented with inverter, 2 AND gates and OR gate: i i z c Sum of products is not practical for circuits it with large number of s (n) Gates with more than 3 s are not practical to build The number of possible products can be proportional to 2 n Inf2C (Computer Systems)
4 /24/28 Arithmetic circuits 32-bit adder Full adder: a b a a 3 c c 64 s too complex for sum of b b 3 c 3 products carry(-out) sum c(carr (carry-in) sum = abc + abc + abc + abc carry = bc + ac + ab a b c carry sum Inf2C (Computer Systems) Ripple carry adder 32-bit adder: chain of 32 full adders a 3 b 3 c 3 a b c a b c bit full-adder s 32 s 3 s s Result bits (S i ) are computed in seuence (S, S,, S 3 ) as Si depends on C i, which in turn reuires S i- to be computed Inf2C (Computer Systems)
5 /24/28 Propagation Delays Propagation delay = time delay between signal arrival and signal arrival at the other end Dl Delay depends d on technology (transistor, it wire capacitance, etc) and number of gates driven by the gate s (fan out) eg: Sum of products circuits: 3 2- gate delays (inverter, AND, OR) very fast! eg: 32-bit ripple carry adder: gate delays ( AND + OR for each of 3 carries to propagate; inverter + AND + OR for S 3 ) slow Inf2C (Computer Systems) Seuential circuits combinational feedback seuential Output depends on current s as well as past s The circuit has memory Seuences of s generate seuences of s seuential Inf2C (Computer Systems)
6 /24/28 Seuential circuits For a fixed and n feedback signals, the circuit can have 2 n possible different behaviours (states) Eg Eg n= one state if feedback signal = one state if feedback signal = Example: SR latch S Inputs: R, S Feedback: Output: R Inf2C (Computer Systems) SR Latch Truth table: S R i u=unused Usage: -bit memory i- u S R Keep the value in memory by maintaining S= and R= Set the value in memory to (or ) by setting R= (or S=) for a short time S = S = R R Inf2C (Computer Systems)
7 /24/28 Timing of events Asynchronous seuential State (and possibly ) of circuit changes whenever s change Synchronous seuential State (and possibly ) can only change at times synchronized to an external signal the Inf2C (Computer Systems) D flip-flop D D Edge-triggered flip-flop: on a edge D is copied to Can be used to build registers: D 3 3 D 3 3 D 2 2 D 4-bit register D 2 D 2 D D Inf2C (Computer Systems)
8 /24/28 General seuential circuit Current state signals combinational m D m D Next state signals Operation: At every rising i edge next state t signals are propagated to current state signals Current state signals plus s work through combinational and generate and next state signals Inf2C (Computer Systems) Hardware FSM A seuential circuit is a (deterministic) Finite State Machine FSM Example: Vending machine Accepts p, 2p coins, sells one product costing 3p, no change given Coin reader has 2 s: a,b for p, 2p coins respectively Output z asserted when 3p or more has been paid in Inf2C (Computer Systems)
9 /24/28 a b FSM implementation Methodology: Choose encoding for states, eg S=,, S3= Build truth th table for the next state te s ', s ' and ndotptz Generate euations for s ', s ', z Design comb from euations and add stateholding register s s a b s ' s ' z comb z S S S ' S ' clk Inf2C (Computer Systems)
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