Combinational Logic Design

Transcription

1 PEN 35 - igital System esign ombinational Logic esign hapter 3 Logic and omputer esign Fundamentals, 4 rd Ed., Mano 2008 Pearson Prentice Hall esign oncepts and utomation top-down design proceeds from an abstract, highlevel specification to a more and more detailed design by decomposition and successive refinement bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks esigns usually proceed from both directions simultaneously Top-down design answers: What are we building? ottom-up design answers: How do we build it? Top-down controls complexity while bottom-up focuses on the details

2 esign Example X 0 X X 2 X 3 X 4 X 5 X 6 X 7 X 8 9-Input odd function Z O (a) Symbol for circuit X 0 X X Input odd function 2 O X 3 X 4 X Input odd function 2 O 0 3-Input odd function 2 O Z O X 6 X 7 X Input odd function 2 O (b) ircuit as interconnected 3-input odd function blocks 0 O 2 (c) 3-input odd function circuit as interconnected exclusive-or blocks (d) Exclusive-OR block as interconnected NNs Reusable Functions and Whenever possible, we try to decompose a complex design into common, reusable function blocks These blocks are verified and well-documented placed in libraries for future use Representative omputer-ided esign Tools: Schematic apture Logic Simulators Timing Verifiers Hardware escription Languages Verilog and VHL Logic Synthesizers Integrated ircuit Layout 2

3 Integrated ircuits Integrated circuit (informally, a chip ) is a semiconductor crystal (most often silicon) containing the electronic components for the digital gates and storage elements which are interconnected on the chip. Terminology - Levels of chip integration SSI (small-scale integrated) - fewer than 0 gates MSI (medium-scale integrated) - 0 to 00 gates LSI (large-scale integrated) - 00 to thousands of gates VLSI (very large-scale integrated) - thousands to 00s of millions of gates ULSI (Ultra large-scale integration) 00 million to billion(s) ombinational ircuits combinational logic circuit has: set of m oolean inputs, set of n oolean outputs, and n switching functions, each mapping the 2 m input combinations to an output such that the current output depends only on the current input values block diagram: ombinatorial Logic ircuit m oolean Inputs n oolean Outputs 3

4 Simplification with on t care conditions There are applications in which the function is not specified for certain input combinations: - Input combinations never occur - Input combinations are expected to occur but we simply don t care what the outputs are in response to the input combinations. These conditions can be used on a map to provide further simplification of the function. Simplification with on t care conditions (example) F(,,, ) = m(,3,7,,5 ) d(,,, ) = m(0,2,5) x x F (,,, ) = m(,3,7,,5 ) x x x x F = + '' F = + ' ' F = + ' 4

5 Multi-Level ircuit Optimization Multi-Level circuits can reduce the cost of ombinational Logic ircuits. G = + + E + F + F Gate-Input ost = 7 Multi-Level ircuit Optimization (continued) G = + + E + F + F G = ( + ) + E + ( + ) F Gate-Input ost = 3 5

6 Multi-Level ircuit Optimization (continued) G = + + E + F + G = ( + F)( + ) + E F Gate-Input ost = Multi-Level ircuit Optimization (continued) G = + + E + F + G = ( + F)( + ) + E G = ( + F)( + ) + E F Gate-Input ost = 9 6

7 High-Impedance Outputs Tri-State uffer Transmission Gate Transmission Gate Logic Technology Parameters Specific gate implementation technologies are characterized by the following parameters: Fan-in the number of inputs available on a gate Fan-out the number of standard loads driven by a gate output ost The cost of a gate is proportional to the chip area occupied by the gate Logic Levels the signal value ranges for and 0 on the inputs and and 0 on the outputs (see Figure -) Noise Margin the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output Propagation elay the time for a change on an input of a gate to propagate to the output. Power issipation the amount of power drawn from the power supply and consumed by the gate 7

8 Propagation elay in hapter 6 Propagation delay is the time for a change on an input of a gate to propagate to the output. elay is usually measured at the 50% point with respect to the H and L output voltage levels. High-to-low (t PHL ) and low-to-high (t PLH ) output signal changes may have different propagation delays. High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input. n HL input transition causes: an LH output transition if the gate inverts and an HL output transition if the gate does not invert. Propagation elay (continued) logic gate always takes some time to change states t PLH is the delay time before output changes from low to high t PHL is the delay time before output changes from high to low both t PLH & t PHL are measured between the 50% points on the input and output transitions INPUT 50% OUTPUT t PHL t pd = max (t PHL, t PLH ) t PLH 8

9 Propagation elay (continued) Find t PHL, t PLH and t pd for the signals given.5 ns IN (volts) OUT (volts).0 ns per division t (ns) Fan-out and elay The fan-out loading a gate s output affects the gate s propagation delay (input-to-output) Example: One realistic equation for t pd for a NN gate with 4 inputs is: t pd = SL ns SL is the number of standard loads the gate is driving. ssume SL = 4.5, t pd = 0.65 ns 9

10 Fan-out and elay - example 4-input NN gate is attached to the inputs of the following gates with a given number of standard loads representing their inputs: 4-input NOR gate (0.8 standard load) 3-input NN gate (.00 standard load) t pd = SL ns (4-input NN gate) What is the total t pd? 0. ns Note that in modern high-speed designs, the portion of gate delay due to wiring capacitance is often significant. Fan-in For high-speed technologies fan-in, the number of inputs to a gate is often restricted to no more than 4 or 5. Problem: Implement a 7-input NN gate using NN gates with 4 inputs. 0

11 ost In an integrated circuit: The cost of a gate is proportional to the chip area occupied by the gate The gate area is roughly proportional to the number and size of the transistors and the amount of wiring connecting them If the actual chip area occupied by the gate is known, it is a far more accurate measure. Speed-Power Product Speed (propagation delay) and power consumption are the two most important performance parameters of a digital I. simple means for measuring and comparing the overall performance of an I family is the speed-power product (the smaller, the better). For example, an I has an average propagation delay of 0 ns and an average power dissipation of 5 mw. What is the speed-power product? 50 pico joules

12 esign Procedure. Specification Write a specification for the circuit if one is not already available 2. Formulation erive a truth table or initial oolean equations that define the required relationships between the inputs and outputs, if not in the specification 3. Optimization pply 2-level and multiple-level optimization raw a logic diagram or provide a netlist for the resulting circuit using Ns, ORs, and inverters esign Procedure 4. Technology Mapping Map the logic diagram or netlist to the implementation technology selected 5. Verification Verify the correctness of the final design 2

13 esign Example. Specification to Excess-3 code converter Transforms code for the decimal digits to Excess-3 code for the decimal digits code words for digits 0 through 9: 4-bit patterns 0000 to 00, respectively Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 00) added to each code word Implementation: multiple-level circuit NN gates (including inverters) esign Example (continued) 2. Formulation onversion of 4-bit codes can be most easily formulated by a truth table Variables - :,,, Variables - Excess-3 W,X,Y,Z on t ares - 00 to Input Output Excess-3 WXYZ

14 esign Example (continued) 3. Optimizationz a. 2-level using K-maps W = + + X = + + Y = + Z = x X X X X X X y w X X X X X X X X X X X X X X X X X X esign Example (continued) 3. Optimization (continued) b. Multiple-level using transformations W = + + X = + + Y = + Z = G = = 23 Perform extraction, finding factor: T = + W = + T X = T + Y = + Z = G = = 9 4

15 esign Example (continued) 3. Optimization (continued) b. Multiple-level using transformations T = + W = + T X = T + Y = + Z = G = 9 n additional extraction not shown in the text since it uses a oolean transformation: ( = + = T ): W = + T X = T + T Y = + T Z = G = = 6 esign Example (continued) 4. Technology Mapping Mapping with a library containing inverters and 2-input NN, 2-input NOR, and 2-2 OI gates W W X X Y Y Z Z 5

16 Technology Mapping hip design styles ells and cell libraries Mapping Techniques NN gates NOR gates Multiple gate types Programmable logic devices The subject of hapter 3 - Part 2 hip esign Styles Full custom - the entire design of the chip down to the smallest detail of the layout is performed Expensive Justifiable only for dense, fast chips with high sales volume Standard cell - blocks have been designed ahead of time or as part of previous designs Intermediate cost Less density and speed compared to full custom Gate array - regular patterns of gate transistors that can be used in many designs built into chip Lowest cost Less density compared to full custom and standard cell 6

17 ell Libraries ell - a pre-designed primitive block ell library - a collection of cells available for design using a particular implementation technology ell characterization - a detailed specification of a cell for use by a designer - often based on actual cell design and fabrication and measured values ells are used for gate array, standard cell, and in some cases, full custom chip design Example ell Library ell Name ell Schematic Normalized rea Typical Input Load Typical Input-to- Output elay asic Function Templates Inverter NN x SL x SL 2NOR x SL 2-2 OI x SL 7

18 Mapping to NN gates ssumptions: Gate loading and delay are ignored ell library contains an inverter and n-input NN gates, n = 2, 3, n N, OR, inverter schematic for the circuit is available The mapping is accomplished by: Replacing N and OR symbols, Pushing inverters through circuit fan-out points, and anceling inverter pairs NN Mapping lgorithm (Example) E (a) F E 7 8 Y 5 X 3 (b) 6 OI F 5 7 Y X 5 6 F E (c) (d) 8

19 NOR Mapping Example F X 3 2 F E (a) E (b) F E (c) Verification Verification - show that the final circuit designed implements the original specification Simple specifications are: truth tables oolean equations HL code If the above result from formulation and are not the original specification, it is critical that the formulation process be flawless for the verification to be valid! 9

20 asic Verification Methods Manual Logic nalysis Find the truth table or oolean equations for the final circuit ompare the final circuit truth table with the specified truth table, or Show that the oolean equations for the final circuit are equal to the specified oolean equations Simulation Simulate the final circuit (or its netlist, possibly written as an HL) and the specified truth table, equations, or HL description using test input values that fully validate correctness. The obvious test for a combinational circuit is application of all possible care input combinations from the specification Verification Example: Simulation Enter -to-excess-3 ode onverter ircuit Schematic INV W NN2 NN2 NOR2 INV INV NN2 X INV NN3 NN2 INV N2 Y NOR2 N2 OI Z 20

21 Verification Example: Simulation Enter waveform that applies all possible input combinations: INPUTS 0 50 ns 00 ns 2