INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC0 74C/CT/CU/CMOS ogic Family Specifications The IC0 74C/CT/CU/CMOS ogic Package Information The IC0 74C/CT/CU/CMOS ogic Package Outlines File under Integrated Circuits, IC0 December 1990

2 FEATURES Two 4-bit binary counters with individual clocks Divide-by any binary module up to 28 in one package Two master resets to clear each 4-bit counter individually Output capability: standard I CC category: MSI GENERA DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (1MR and 2MR) inputs to each counter. The operation of each half of the 393 is the same as the 93 except no external clock connections are required. The counters are triggered by a IG-to-OW transition of the clock inputs. The counter outputs are internally connected to provide clock inputs to succeeding stages. The outputs of the ripple counter do not change synchronously and should not be used for high-speed address decoding. The master resets are active-ig asynchronous inputs to each 4-bit counter identified by the 1 and 2 in the pin description. A IG level on the nmr input overrides the clock and sets the outputs OW. QUICK REFERENCE DATA GND = 0 V; T amb = 2 C; t r = t f = ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay C = 1 pf; V CC = V ncp to nq 0 12 ns nq to nq n+1 ns nmr to nq n 11 1 ns f max maximum clock frequency 99 3 Mz C I input capacitance pf C PD power dissipation capacitance per counter notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1. V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December

3 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1, 13 1CP, 2CP clock inputs (IG-to-OW, edge-triggered) 2, 12 1MR, 2MR asynchronous master reset inputs (active IG) 3, 4,,, 11, 10, 9, 8 1Q 0 to 1Q 3, 2Q 0 to 2Q 3 flip-flop outputs 7 GND ground (0 V) V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December

4 Fig.4 Functional diagram. Fig. State diagram. COUNT SEQUENCE FOR 1 COUNTER COUNT OUTPUTS Q 0 Q 1 Q 2 Q 3 Fig. ogic diagram (one counter). Notes 1. = IG voltage level = OW voltage level December

5 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r = t f = ns; C = 0 pf SYMBO t P / t P t P / t P t P PARAMETER propagation delay 41 ncp to nq propagation delay nq n to nq n+1 4 propagation delay 39 nmr to nq n 11 t T / t T output transition time 19 7 t rem f max clock pulse width IG or OW master reset pulse width; IG removal time nmr to ncp maximum clock pulse frequency T amb ( C) 74C to to +12 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) Mz WAVEFORMS December 1990

6 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT 1CP 2CP 1MR 2MR UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = 0 V; t r = t f = ns; C = 0 pf T amb ( C) TEST CONDITIONS ns ns ns 4. 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +12 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay ncp to nq 0 t P / t P propagation delay nq n to nq n+1 t P propagation delay nmr to nq n t T / t T output transition time ns 4. t rem f max clock pulse width IG or OW master reset pulse width; IG removal time nmr to ncp maximum clock pulse frequency ns 4. 1 ns 4. 0 ns Mz 4. December 1990

7 AC WAVEFORMS (1) C : V M = 0%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the clock (ncp) to output (1Q n,2q n ) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) C : V M = 0%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the master reset (nmr) pulse width, the master reset to output (Q n ) propagation delays and the master reset to clock (ncp) removal time. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic