Announcements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution
|
|
- Cathleen Watts
- 5 years ago
- Views:
Transcription
1 - Fall 2002 Lecture 25 Interconnect Effects I/O, Power Distribution Announcements Homework 9 due next Tuesday Hardware lab this week Project phase 2 due in two weeks 1
2 Today s Lecture Impact of interconnects» I/O» Power distribution Interconnect Issues 2
3 Impact of Interconnect Parasitics Reduce Robustness Affect Performance Classes of Parasitics Capacitive Resistive Inductive INTERCONNECT Dealing with Capacitance 3
4 Capacitive Crosstalk Dynamic Node V DD CLK C XY Y In 1 In 2 In 3 PDN C Y X 2.5 V CLK 0 V 3 x 1 µm overlap: 0.19 V disturbance Capacitive Crosstalk Driven Node X R C τ Y XY = R Y (C XY +C Y ) XY V 0.3 X Y t r C 0.25 Y V (Volt) Keep time-constant smaller than rise time t(sec) x
5 Delay Degradation C c - Impact of neighboring signal activity on switching delay - When neighboring lines switch in opposite direction of victim line, delay increases Miller Effect - Both terminals of capacitor are switched in opposite directions (0 V dd, V dd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV) Interconnect Projections Low-k dielectrics Both delay and power are reduced by dropping interconnect capacitance Types of low-k materials include: inorganic (SiO 2 ), organic (Polyimides) and aerogels (ultra low-k) The numbers below are on the conservative side of the NRTS roadmap e Generation 0.25 µm 0.18 µm 0.13 µm 0.1 µm 0.07 µm 0.05 µm Dielectric Constant
6 How to Battle Capacitive Crosstalk Shielding wire GND V DD GND Shielding layer Avoid large crosstalk cap s Avoid floating nodes Isolate sensitive nodes Control rise/fall times Shield! Differential signalling Substrate (GND) Driving Large Capacitances t phl = C L V swing /2 V DD I av V in C L V out Transistor Sizing 6
7 Using Cascaded Buffers In Out 1 2 N C L = 20 pf 0.25 mm process Cin = 2.5 ff tp0 = 30 ps F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns Output Driver Design Trade off Performance for Area and Energy» Given t pmax find N and f Area A driver Energy E driver = = N 2 N 1 f 1 F 1 ( 1+ f + f f ) Amin = Amin = Amin f 1 f 1 2 N 1 2 F 1 2 CL 2 ( + f + f f ) C V = C V V 1 i DD i DD DD f 1 f 1 7
8 Output Driver Design 0.25 mm process, C L = 20 pf Transistor Sizes for optimally-sized cascaded buffer t p = 0.76 ns Transistor Sizes of redesigned cascaded buffer t p = 1.8 ns Reducing the swing t phl = C L V swing /2 I av Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Delay penalty is paid by the receiver Requires use of sense amplifier to restore signal level Frequently designed differentially (e.g. LVDS) 8
9 Tristate Buffers V DD V DD En In En Out Out En In En How to Design Large Transistors D(rain) Multiple Contacts Reduces diffusion capacitance S(ource) G(ate) small transistors in parallel 9
10 Bonding Pad Design Bonding Pad GND 100 µm Out V DD In GND Out ESD Protection V DD PAD R D1 D2 X C Diode 10
11 ESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate need guard rings to pick it up. Chip Packaging L Bonding wire L Chip Lead frame Mounting cavity Bond wires (~25µm) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100µm in 0.25µm technology), with large pitch (100µm) Pin Many chips areas are pad limited 11
12 Pad Frame Layout Die Photo Chip Packaging An alternative is flip-chip :» Pads are distributed around the chip» The soldering balls are placed on pads» The chip is flipped onto the package» Can have many more pads 12
13 INTERCONNECT Dealing with Resistance Impact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution:» IR drop» Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gates 13
14 RI Introduced Noise V DD I φ pre R V DD - V X V I R V Power and Ground Distribution V DD GND Logic Logic V DD V DD GND (a) Finger-shaped network GND (b) Network with multiple supply pins 14
15 Resistance and the Power Distribution Problem Before After Requires fast and accurate peak current prediction Heavily influenced by packaging technology Source: Simplex Power Distribution Low-level distribution is in Metal 1 Power has to be strapped in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on straps 15
16 Electromigration (1) Limits dc-current to 1 ma/µm Electromigration (2) 16
17 The Impact of Resistivity T r The distributed rc-line R 1 R 2 R N-1 R N C 1 C 2 C N-1 C N V in Diffused signal propagation Delay ~ L 2 voltage (V) voltage (V) x= L/10 x= L/10 x = L/4 x = L/4 x = L/2 x = L/2 x= L x= L time (nsec) time (nsec) d The Global Wire Problem w w ( R C + R C R C ) T = 0.377R C Challenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions» Use of fat wires» Insert repeaters but might become prohibitive (power, area)» Efficient chip floorplanning Towards communication-based design» How to deal with latency?» Is synchronicity an absolute necessity? d out d w w out 17
18 Reducing RC-delay Repeater Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: Tins r = 2.2 mw-cm M6 Increasing die size and device count: we need more wires and longer wires to connect everything W S M5 Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC H M4 3.5 Minimum Widths (Relative) 4.0 Minimum Spacing (Relative) substrate M3 M2 M1 poly 0.25 µm wiring stack m 0.8m 0.6m 0.35m 0.25m M5 M4 M3 M2 M1 Poly m 0.8m 0.6m 0.35m 0.25m M5 M4 M3 M2 M1 Poly 18
19 Interconnect Projections: Copper Copper is planned in full sub-0.25 µm process flows and large-scale designs (IBM, Motorola, IEDM97) With cladding and other effects, Cu ~ 2.2 µω-cm vs. 3.5 for Al(Cu) 40% reduction in resistance Electromigration improvement; 100X longer lifetime (IBM, IEDM97)» Electromigration is a limiting factor beyond 0.18 µm if Al is used (HP, IEDM95) Vias INTERCONNECT Dealing with Inductance 19
20 Common Wire Cross-Sections Coaxial Cable Triplate Strip Line MicroStrip Wire above Ground Plane 2πε c = log r2 r1 µ l = log 2π r2 r1 ε c = h W h l = µ W cl = εµ c - capacitance/length l - inductance/length L di/dt Vin V DD L V DD i(t) V out Impact of inductance on supply voltages: Change in current induces the change in voltage Longer supply lines have larger L C L GND L 20
21 L di/dt: Simulation 5.0 v out 5V t V out (V) t fall = 4 nsec t fall = 0.5 nsec i L 40mA 20mA t I L (ma) v L V t V L (V) t (nsec) Signals Waveforms for Output Driver connected To Bonding Pads (a) v out ; (b) i L and (c) v L. The Results of an Actual Simulation are Shown on the Right Side. Choosing the Right Pin Bonding wire L Chip Mounting cavity L Lead frame Pin 21
22 Decoupling Capacitors Board wiring Bonding wire SUPPLY C d CHIP Decoupling capacitor Decoupling capacitors are added: on the board (right under the supply pins) on the chip (under the supply straps, near large buffers) De-coupling Capacitor Ratios EV4» total effective switching capacitance = 12.5nF» 128nF of de-coupling capacitance» de-coupling/switching capacitance ~ 10x EV5» 13.9nF of switching capacitance» 160nF of de-coupling capacitance EV6» 34nF of effective switching capacitance» 320nF of de-coupling capacitance -- not enough! Source: B. Herrick (Compaq) 22
23 EV6 De-coupling Capacitance Design for Idd= 25 Vdd = 2.2 V, f = 600 MHz» 0.32-µF of on-chip de-coupling capacitance was added Under major busses and around major gridded clock drivers Occupies 15-20% of die area» 1-µF 2-cm 2 Wirebond Attached Chip Capacitor (WACC) significantly increases Near-Chip decoupling 160 Vdd/Vss bondwire pairs on the WACC minimize inductance Source: B. Herrick (Compaq) EV6 WACC 389 Signal VDD/VSS Pins 389 Signal Bondwires 395 VDD/VSS Bondwires 320 VDD/VSS Bondwires WACC Microprocessor Heat Slug 587 IPGA Source: B. Herrick (Compaq) 23
24 Design Techniques to address L di/dt Separate power pins for I/O pads and chip core Multiple power and ground pins Position of power and ground pins on package Increase tr and tf Advanced packaging technologies Decoupling capacitances on chip and on board The Transmission Line V in r l r l r l x r l V out g c g c g c g c The Wave Equation 24
25 Lossless Transmission Line - Parameters speed of light in vacuum Wave Propagation Speed 25
26 Wave Reflection for Different Terminations Transmission Line Response (R L = ) V V Dest V Source R S = 5Z 0 (a) V R S = Z 0 (b) V R S = Z 0 / t (in t lightf ) (c) 26
27 Lattice Diagram V Source V Dest V V V V t V V V V... L/ν Critical Line Lengths versus Rise Times L crit ~ 1cm ps today (1990, Bakoglu) 27
28 Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ). t r (t f ) << 2.5 t flight Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z 0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z 0 /2 Should we be worried? Transmission line effects cause overshooting and nonmonotonic behavior Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) [Restle98] 28
Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics
Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance
More information10/16/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter VI Coping with Interconnect 1 Impact of Interconnect Parasitics Reduce Robustness Affect Performance Increase delay Increase power dissipation Classes of Parasitics
More informationLecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect
Lecture 25 Dealing with Interconnect and Timing Administrivia Projects will be graded by next week Project phase 3 will be announced next Tu.» Will be homework-like» Report will be combined poster Today
More informationEE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires
EE141-Spring 2008 Digital Integrated Circuits Lecture 24: Wires 1 Announcements Hw 8 posted last graded homework Project phase II feedback to be expected anytime 2 Material Last Lecture: Wire capacitance
More informationEE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire
EE141-Spring 2007 Digital Integrated Circuits ecture 10 Administrative Stuff No ab this week Midterm 1 on Tu! HW5 to be posted by next Friday Due Fr. March 2 5pm Introduction to wires 1 2 ast ecture ast
More informationInterconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003
Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class
More informationInterconnect s Role in Deep Submicron. Second class to first class
Interconnect s Role in Deep Submicron Dennis Sylvester EE 219 November 3, 1998 Second class to first class Interconnect effects are no longer secondary # of wires # of devices More metal levels RC delay
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More information! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationDigital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.
Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact
More informationLecture 21: Packaging, Power, & Clock
Lecture 21: Packaging, Power, & Clock Outline Packaging Power Distribution Clock Distribution 2 Packages Package functions Electrical connection of signals and power from chip to board Little delay or
More informationInterconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive
More information10. Performance. Summary
10. Performance Summary Interconnect Parameters: Capacitance, Resistance, Inductance Electrical Wire Models Lumped C model Lumped RC model RC chain model Distributed RC line model Transmission line model
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationInterconnects. Introduction
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER
More informationThe Wire EE141. Microelettronica
The Wire 1 Interconnect Impact on Chip 2 Example: a Bus Network transmitters receivers schematics physical 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics Interconnect
More informationVLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationThe Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on
More informationAnnouncements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationSRAM System Design Guidelines
Introduction This application note examines some of the important system design considerations an engineer should keep in mind when designing with Cypress SRAMs. It is important to note that while they
More informationPDN Planning and Capacitor Selection, Part 1
by Barry Olney column BEYOND DESIGN PDN Planning and Capacitor Selection, Part 1 In my first column on power distribution network (PDN) planning, Beyond Design: Power Distribution Network Planning, I described
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationECE 497 JS Lecture - 18 Impact of Scaling
ECE 497 JS Lecture - 18 Impact of Scaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday April 8 th Speaker: Prof.
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low Power-Low Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks - 3/7 by 5pm
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 13, 2017 Variation; I/O Circuits, Inductive Noise Lecture Outline! Design Quality " Variation! Packaging! Variation and Testing!
More informationSemiconductor memories
Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationDigital Integrated Circuits (83-313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1
Digital Integrated Circuits (83-313) Lecture 5: Interconnect Semester B, 2015-16 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 What will we learn today? 1 A First Glance at Interconnect 2 3
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationAnnouncements. EE141- Spring 2003 Lecture 8. Power Inverter Chain
- Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :30-3pm at BWRC (in lieu of Tuesday) Today s lecture Power
More informationThe Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003 Propagation Delay CMOS
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 3 Circuit Optimization for Speed Announcements Tu 2/8/00 class will be pre-taped on Friday, 2/4, 4-5:30 203 McLaughlin Class notes are available
More informationCMOS Transistors, Gates, and Wires
CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationPreamplifier in 0.5µm CMOS
A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling
More informationECE 451 Transmission Lines & Packaging
Transmission Lines & Packaging Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Radio Spectrum Bands The use of letters to designate bands has long ago
More informationCMPEN 411 VLSI Digital Circuits Spring 2012
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
More informationCSE241 VLSI Digital Circuits Winter Lecture 07: Timing II
CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns
More informationE40M Capacitors. M. Horowitz, J. Plummer, R. Howe
E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast
More informationLecture 8-1. Low Power Design
Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@ic.ac.uk Lecture 8-1 Based on slides/material
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationEEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationTransmission Lines. Author: Michael Leddige
Transmission Lines Author: Michael Leddige 1 Contents PCB Transmission line structures Equivalent Circuits and Key Parameters Lossless Transmission Line Analysis Driving Reflections Systems Reactive Elements
More informationLecture 9: Interconnect
Digital Integrated Circuits (83-313) Lecture 9: Interconnect Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety,
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18-322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The check-off is due today (by 9:30PM) Students
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationLecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM
Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/27/18 VLSI-1 Class Notes Why Clocking?
More informationPower Consumption in CMOS CONCORDIA VLSI DESIGN LAB
Power Consumption in CMOS 1 Power Dissipation in CMOS Two Components contribute to the power dissipation:» Static Power Dissipation Leakage current Sub-threshold current» Dynamic Power Dissipation Short
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN70: High-Speed Links Circuits and Systems Spring 07 Lecture : Channel Components, Wires, & Transmission Lines Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab Lab begins
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
More informationNTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,
More informationEECS 151/251A Homework 5
EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis
EE115C Winter 2017 Digital Electronic Circuits Lecture 19: Timing Analysis Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop-
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999
UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma
More informationECE414/514 Electronics Packaging Spring 2012 Lecture 6 Electrical D: Transmission lines (Crosstalk) Lecture topics
ECE414/514 Electronics Packaging Spring 2012 Lecture 6 Electrical D: Transmission lines (Crosstalk) James E. Morris Dept of Electrical & Computer Engineering Portland State University 1 Lecture topics
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS0026 Dual High-Speed MOS Driver General Description DS0026 is a low cost
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationEE115C Digital Electronic Circuits Homework #6
Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages
More informationEECS 151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: Nick Weaver & John Wawrzynek. Lecture 12 EE141
EECS 151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: Nick Weaver & John Wawrzynek Lecture 12 1 Wire Models All-inclusive model Capacitance-only 2 Capacitance Capacitance: The Parallel
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationECE 497 JS Lecture - 18 Noise in Digital Circuits
ECE 497 JS Lecture - 18 Noise in Digital Circuits Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday April 15 th Speaker:
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationLecture 16: Circuit Pitfalls
Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationNTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
More informationMODULE III PHYSICAL DESIGN ISSUES
VLSI Digital Design MODULE III PHYSICAL DESIGN ISSUES 3.2 Power-supply and clock distribution EE - VDD -P2006 3:1 3.1.1 Power dissipation in CMOS gates Power dissipation importance Package Cost. Power
More informationECE260B CSE241A Winter Interconnects. Website:
ECE260B CSE241A Winter 2004 Interconnects Website: http://vlsicad.ucsd.edu/courses/ece260b-w04 ECE 260B CSE 241A Interconnects 1 Outline Interconnects Resistance Capacitance and Inductance Delay ECE 260B
More informationLast Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
More informationResearch Challenges and Opportunities. in 3D Integrated Circuits. Jan 30, 2009
Jan 3, 29 Research Challenges and Opportunities in 3D Integrated Circuits Ankur Jain ankur.jain@freescale.com, ankurjain@stanfordalumni.org Freescale Semiconductor, Inc. 28. 1 What is Three-dimensional
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic
More informationEE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor
More informationEE141. Administrative Stuff
-Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw
More informationNext, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on May 1, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu) Prof. Jan Rabaey EECS
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationThe Linear-Feedback Shift Register
EECS 141 S02 Timing Project 2: A Random Number Generator R R R S 0 S 1 S 2 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 The Linear-Feedback Shift Register 1 Project Goal Design a 4-bit LFSR SPEED, SPEED,
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationInterconnects and Reliability
Interconnects and Reliability Sandip Tiwari st222@cornell.edu Logic Interconnects SRAM: IBM J. R&D (1995) Insulators/Reliability 1 Prologue Global Middle Local 2 Interconnects Fringing & Coupling Capacitances
More informationCPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration
CPE/EE 427, CPE 527 VLSI Design I L3: Wires, Design for Speed Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-05f
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationCMOS Logic Gates. University of Connecticut 172
CMOS Logic Gates University of Connecticut 172 Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationDATASHEET CD40109BMS. Features. Description. Applications. Functional Diagram. Pinout. CMOS Quad Low-to-High Voltage Level Shifter
DATASHEET CD19BMS CMOS Quad Low-to-High Voltage Level Shifter Features High Voltage Type (V Rating) Independence of Power Supply Sequence Considerations - can Exceed - Input Signals can Exceed Both and
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationDynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect
Wright State University CORE Scholar Browse all Theses and Dissertations Theses and Dissertations 2014 Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect
More information