The Wire EE141. Microelettronica

Transcription

1 The Wire 1

2 Interconnect Impact on Chip 2

3 Example: a Bus Network transmitters receivers schematics physical 3

4 Wire Models All-inclusive model Capacitance-only 4

5 Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive 5

6 Capacitance: The Parallel Plate Model L Current flow W Electrical-field lines H t di Dielectric Substrate c int = ε t di di WL S Cwire = S S S L = 1 S L 6

7 Permittivity 7

8 Fringing Capacitance c fringe c pp (a) H W - H/2 + (b) 8

9 Fringing versus Parallel Plate 9

10 Interwire Capacitance fringing parallel 10

11 Impact of Interwire Capacitance 11

12 Wiring Capacitances (0.25 μm CMOS) 12

13 Interwire Capacitance between parallel wires (0.25 μm CMOS) 13

14 Wire Resistance R = ρ L H W H L Sheet Resistance R o W R 1 R 2 14

15 Interconnect Resistance 15

16 Sheet Resistance 16

17 Polycide Gate MOSFET Silicide PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly 17

18 Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length 18

19 Modern Interconnect 19

20 Skin effect 20

21 Skin Effect and Aluminum Wires (H=0.7 μm) 21

22 Inductance Voltage drop : l, c inductance and capacitance (per unit lenght) of a wire Propagation speed : 22

23 Dielectric constants and wave propagation speed (μ r 1) 23

24 Interconnect Modeling 24

25 The Lumped Model V out Driver c wi re R driver V out V in C lumped 25

26 The Lumped RC-Model The Elmore Delay s 26

27 The Elmore Delay: : RC Chain 27

28 Wire Model Assume: Wire modeled by N equal-length segments For large values of N: 28

29 The Distributed RC-line 29

30 Step-response of RC wire as a function of time and space x= L/10 voltage (V) x = L/4 x = L/2 x= L time (nsec) x is the distance between the observation point and the source 30

31 RC-Models 31

32 Design Rules of Thumb rc delays should only be considered when t prc t pgate of the driving gate L crit = t pgate /0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC when not met, the change in the signal is slower than the propagation delay of the wire 32

33 Driving an RC-line R s (r w,c w,l) V out V in 33

34 Simulation Models for Distributed RC line 34

35 The Transmission Line V in r l l l l r r x r V out g c g c g c g c The Wave Equation 35

36 Trasmission line with terminating impedences Z S Z 0 Z L 36

37 Trasmission Line Terminations 37

38 Matched Termination Z 0 Z 0 Z L Series Source Termination Z S Z 0 Z 0 Parallel Destination Termination 38

39 Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ). t r (t f ) << 2.5 t flight = 2.5 L wire /υ Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z 0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z 0 / 2 39