Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Transcription

1 Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1

2 Outline Scaling Issues for Planar MOSFET: Subthreshold Slope Drain Induced Barrier Lowering (DIBL) Threshold Voltage Doping effect on: Mobility Junction Leakage due to Band-to-Band Tunneling Junction Capacitance Silicon on Insulator (SOI) Dual Gate FET FinFET EC738 Advanced Devices 2

3 Subthreshold Current and Slope for Planar Long Channel MOSFET At V gs = 0: S = W I ds subth = μ neff C ox L m 1 kt q 2 e q V gs Vt mkt 1 e qvds/kt I ds Off =Off-state leakage current I o e qvt mkt -> Ids leakage increase exponentially with decreasing V t or increasing T d log 10 Ids dv gs 1 Expressed in mv/decade = 2.3 m kt q = 2.3 kt q As L decreases, V t decreases, and both S and I subth degrade 1 + C dm C ox 2.3 kt q 1 + 3t ox W dm One solution is to minimize the body effect coefficient m by decreasing C dm w.r.t. C ox : Double C ox for a given C dm Increasing W dm worsens SCE EC738 Advanced Devices 3

4 Drain-Induced Barrier Lowering and ΔVt From psuedo-2d Analysis the lowering of V t is: V t = 8 m 1 [ Ψ V bi + Vds 11 t ox W dm ] e πl [2(W dm+3t ox )] V t = V to V t The lowering of ΔV t increases exponentially with increasing the ratio of W dm + 3t ox = mw dm w.r.t. L Try to minimize bothw dm and t ox m = 1 + 3t ox /W dm increases with a smallerw dm, but at slower rate because of the 1 term, and because of scaling down of t ox Decreasing ΔV t exponentially by decreasing (W dm + 3t ox ) decreases in turn I off and S Keep L ~2-3 times W dm EC738 Advanced Devices 4

5 Psuedo-2D Analysis of Short Channel Subthreshold Slope S 2.3 mkt q t ox W dm e πl [2(W dm+3t ox )] = S o t ox W dm e πl [2(W dm+3t ox )] Where S o is the long channel value of S Again: Minimize both W dm and t ox Keep L ~2-3 times W dm EC738 Advanced Devices 5

6 S/D Diode Junction Leakage and Capacitance S/D reverse current from bottom of S/D junctions and sidewalls of junction Band-to-band tunneling S/D pn junction depletion capacitance depends as well on area (bottom area + sidewall area) Additional capacitance means higher parasitics and slower FET EC738 Advanced Devices 6

7 S/D Band-to-Band Tunneling Where J B B = K o E V app exp E 0 E Electric Field = E = 2qN A (V app + V bi ) ε si J BB increases exponentially with N A, in addition to the pre-factor Increasing N A to suppress short channel effects (SCE) exponentially increases S/D pn junction leakage current Ec Ev Vbi+Vapp EC738 Advanced Devices 7

8 S/D Depletion Capacitance Dependence on Doping C diode dep = ε si qn A 2(V bi +V ds ) Increasing N A to suppress short channel effects (SCE) increases S/D pn junction depletion capacitance as a factor of N A EC738 Advanced Devices 8

9 Fully Depleted Silicon-on-Insulator (FD-SOI) Solves one of the problems: limit W dm w.r.t. L Solves the junction leakage and capacitance EC738 Advanced Devices 9

10 FinFET: Dual Gate Doubles the control of the gate over the depletion region Double the channel Width using same footprint: higher W/L Controlled depletion width, independent from doping Allows near-intrinsic doping: higher mobility EC738 Advanced Devices 10

11 Dual Gate FinFET Drain Gate Dielectric L Silicon (depletion) W/2 Wafer Source Top View Gate Electrode EC738 Advanced Devices 11

12 New W dm and xj Drain W fin W dm = H fin 2 x j = H fin 2 L W dm x j Source Top View EC738 Advanced Devices 12

13 Solution of S/D Leakage and Capacitance by Dual Gate FET The leakage current from the bottom area of the S/D have been totally eliminated Only one sidewall contributes to leakage in each junction Possible reduction in substrate doping to near cm, since W dm is not controlled by N A any more Reduction in Band-to-Band tunneling current for S/D EC738 Advanced Devices 13

14 Doping Effect on Mobility Effective mobility (both for bulk and surface) decreases with increasing substrate doping NA Increasing N A to suppress short channel effects (SCE) decreases mobility Surface mobility also degrades more due to increased effective field by increasing NA For Dual Gate FET: Possible reduction in substrate doping to near cm, since W dm is not controlled by N A any more This increases mobility and current EC738 Advanced Devices 14

15 Triple Gate: FinFET Gate and dielectric on top as well W/2 Wafer EC738 Advanced Devices 15

16 Metal Gate / High-k Dielectrics Metal Gates Eliminates polysilicon gate depletion: smaller electrical t oxe Improves the gate resistance, especially RC distributed effect High-k Dielectrics Thicker physical thickness can be used to achieve an equivalent thinner oxide thickness since it has higher dielectric constant: Less gate leakage Standardized on HfO 2 wit ε r 25 t dielectric = t oxide Achieves total equivalent oxide t ox < 1nm Typically a thin (0.5nm) SiO 2 interface layer (IL) with silicon EC738 Advanced Devices 16