Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Transcription

1 EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur 44

2 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive components such as resistor, capacitor and inductor also. Passive components are in general much more difficult to implement as compared to the transistor. Let us consider some of the different ways of implementing a resistor. One can use different layers for fabricating a resistor. Consider the N + /P + source/drain diffused region as illustrated below: N-well P + P-Silicon Among the important SiO 2 characteristics of a resistive layer FOX is its sheet resistance ( sh) ) defined as : R L A sh L W 45

3 A large value of sheet resistance means that a smaller L/W ratio and thus a smaller Silicon area (~WxL) would be required to implement the resistor The sheet resistance of a N + region for 0.5 m technology is ~2.3Ω/ To understand the full implications of this number, consider the implementation of a 100kΩ resistor. For W=1μm, L ~ 10 4 μm would be required. The area of ~10 4 μm 2 is orders of magnitude larger than a typical area of a MOS transistor (W/L = 2/1) This shows that large values of resistors are difficult toimplement on Silicon and that resistors are much more expensive than resistors in terms of chip area. This is one reason why MOS transistors are used as resistors wherever possible 46

4 47

5 Besides sheet resistance, there are other parameters of importance such as temperature coefficient:. R R O ( 1 TCR ( T TO )) TC R 1 R dr dt Temperature coefficient is often specified in units of PPM/ o C. For F the N + /P + resistor, the value could be ~1500PPM/ o C. This means that t the resistor value may change by ~27% for a change in temperature of -55 to 125 o C. The resistor value is in general a function of average voltage applied across it. This is described by voltage coefficient VC R dr 1 R RO ( 1 VCR ( V VO )) R dv Voltage coefficient i is often specified in units of PPM/V. For the N + /P + resistor, the value could be ~200PPM/ V 48

6 The reason for voltage dependence is the presence of PN junction between diffused region and bulk as illustrated below: P + FOX Depletion region N-Well P-Silicon As the voltage across the PN junction changes, the extension of depletion width into N + region also changes. This changes the effective thickness of the N + region and thus its sheet resistance. Because N + is heavily doped, the extension of depletion width into this region is small. As a result voltage coefficient has a smaller value. 49

7 The resistor fabricated using the source diffused layer is not a pure resistor but has a capacitance associated with it as illustrated below: P + FOX Depletion region N-well P-Silicon C~0.93 ff / m 2 The capacitance is due to reverse biased PN junction capacitance. The resistor is thus in fact an RC transmission line whose effects can only be neglected if frequency is below a certain value 50

8 Instead of N + /P + layer, a resistor can be implemented using Poly as the resistive layer: SiO / Poly TC 1500 PPM / o C R sh P-Silicon VC 100 PPM / V R C ~0.086 ff / m 2 High resistivity Poly layer (without silicidation) can be used to obtain an order of magnitude higher values of resistances 51

9 A third way of making a resistor is to use N-well as illustrated below: 726 / sh FOX N + N + TC 8000 PPM / o C P-Silicon N-Well R 4 VC 10 PPM / V R C ~0.095 ff / m 2 This resistor offers high sheet resistance but at the expense of poor TC R and VC R. The voltage coefficient is larger because of smaller doping in the N-well. This makes the extension of depletion width into N-region larger and thus the impact of change in voltage is also larger. A larger well thickness to some extent mitigates t thiseffect. 52

10 Pinched-well resistor N + N + P + FOX P-Silicon N-Well Higher values of sheet resistance can be obtained in this manner 53

11 Passive Components: Capacitor Like a resistor, a capacitor takes up fairly large area. Capacitors with values in nf are virtually impossible to make. Typical capacitors have their values in ~pf. Capacitor/Area, temperature and voltage coefficients, parasitic capacitance and resistance are the parameters against which different ways of fabricating capacitor needs to be evaluated. A simple way of making a capacitor is to use N + layer as shown below: M-1 SiO 2 N + P + P 54

12 P + -n well as a capacitor P + 55

13 Gate-channel Capacitor N + N + FOX The difficulty with this approach is that voltage across the capacitor has to be positive and larger than threshold voltage. Otherwise this technique offers large capacitance/area and reasonably small parasitic capacitance as compared to some of the other approaches P-Silicon Poly 56

14 57

15 If the region under the Poly can also be doped N + as shown below, then one can obtain a much better capacitance. The capacitance is determined primarily determined by the gate-oxide capacitance which is constant. There is no need for an n-well in this case. N + N + N + P-Silicon Poly SiO 2 FOX C ~3.6 ff / m 2 58

16 One might think of implementing a capacitor using the gate oxide as a dielectric in the following manner: C OX N + FOX C Depletion P-Silicon Poly C Parasitic R series N-Well The problem with this capacitor is that it has large parasitics and may have high voltage coefficient if the transistor operates in depletion region as a result of negative gate-source voltage. The presence of a voltage dependent depletion capacitance causes the variation in capacitance value. 59

17 Different metal layers such as M-1, M-2 etc can be used also for making capacitors. Typically these offer much smaller per unit capacitance. C~0.041 ff / m 2 60

18 In some specialized processes there are two Poly layers available. These layers are separated by a thin dielectric which allows easy implementation of a capacitor: 61

19 Layout of poly-poly2 capacitor 62

20 63

21 Inductor M-1 64

22 65

23 On-chip Transformers IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER