10. Performance. Summary

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1 10. Performance Summary Interconnect Parameters: Capacitance, Resistance, Inductance Electrical Wire Models Lumped C model Lumped RC model RC chain model Distributed RC line model Transmission line model Technology Scaling Power and Clock Distribution Input Protection Circuits Static Gate Sizing Off-Chip Driver Circuits Packaging Technology

2 Interconnect Parameters Interconnection choices in an actual CMOS process: multiple layers of Aluminum (up to 7) polysilicon layer (at least one) possibility of using the heavily doped n + and p + layers The wiring forms a complex geometry that introduces parasitics: capacitive resistive inductive Parasitic effects reduce the performance and the reliability by: increasing the propagation delay affecting the energy dissipation and the power distribution introducing extra noise source 3 Modern Interconnect 4

3 Full Wire Model Assume that all wires in a bus network are implemented in a single interconnect layer (Al), isolated from the silicon substrate and from each other by a layer of dielectric material (SiO ): Schematic view Physical view Full wire circuit model: Consider parasitic capacitance, resistance and inductance Parasitics are distributed over the length of the wire Inter-wire parasitics: coupling effects 5 Simplified (Only Capacitance) Wire Model A simplified capacitance-only model can be used if: the wires are short the wires cross-section is large or the wire material has a low resistivity (small resistance) Other simplified models can be obtained 1) Neglecting the inductive effects, valid when: the resistance of the wire is large (long Al wires with a small cross-section) t rise and t fall of the signals are large (slow signals) ) Neglecting the inter-wire capacitance, valid when: the separation between neighboring wires is large the wires run together for a short distance 6

4 Wire Parallel-Plate Capacitance The capacitance of a wire is function of: shape of the wire environment distance to substrate distance to surrounding wires Simple model - the parallel-plate capacitance: C wire C pp ε t ox ox WL H L W Current Flow Electrical-field lines C wire is the total capacitance of the wire (pf) t ox SiO Substrate True for W >> t ox electric field lines are orthogonal to the capacitor plates 7 Wire Fringing Capacitance Advanced processes have a reduced W/H ratio (<1) The capacitance between side-wall of the wires and the substrate (fringing capacitance) must be considered! H W - H/ W + C fringe H SiO Substrate C pp t OX C fringe Substrate C pp c c wire wire c pp + c ( W H ) t fringe ox / ε ox πε + log ( t / H ) c wire is the wire capacity per unit length (pf/cm) For W/H large c fringe < c pp,c wire ~ c pp For W/H < 1.5 c fringe > c pp ox ox c wire c pp c fringe c pp 8

5 Interwire Capacitance Level1 Level C fringe C parallel In multilevel interconnects technologies the wires are not completely isolated Each wire is coupled to the: substrate (grounded capacitor) neighboring wires on the same layer (floating capacitor) neighboring wires on adjacent layers (floating capacitor) Assuming that oxide thickness (t ox 1µm) and metal thickness (H1µm) are held constant while scaling the other dimensions for W < 1.75H, C interwire dominates! 9 Wiring Capacitances Field Active Poly Al1 Al Al3 Al4 Poly Al1 Al Al3 Al4 Al5 Cplate (af/µm) 88 Cfringe (af/µm) 54 Cplate (af/µm) Cfringe (af/µm) Cplate (af/µm) Cfringe (af/µm) Cplate (af/µm) Cfringe (af/µm) Cplate (af/µm) Cfringe (af/µm) Cplate (af/µm) Cfringe (af/µm) Plate and fringe capacitance values for a typical 0.5 µm CMOS process 10

6 Wire Resistance R ρ L H W R L W H L R - Sheet Resistance W R 1 R 11 Dealing With Resistance Selective technology scaling Use better interconnect materials (silicides, bypasses) More interconnect layers (reduce average wire length) Polycide gate MOSFET Silicides: WSi, TiSi, PtSi, TaSi Conductivity: 8-10 times better than Poly 1

7 Other Resistive Effects (1) Contact resistance Extra resistance added by transition between routing layers Can be reduced by making the contact holes larger Current crowding upper limits the size of the contact () Skin effect High frequency (GHz) currents tends to flow on the surface of a conductor Resistance become frequency-dependent (increase when frequency increase) Affects only wider wires (3) Electromigration Limits the DC currents to 1mA/µm 13 Wire inductance At switching frequencies in GHz range the wire inductance must be considered di A changing current passing through an inductor generates a voltage drop: v L dt On-chip inductance effects are: reflection of signals due to impedance mismatch inductive coupling between lines ringing effects switching noise due to Ldi/dt voltage drops It is possible to compute the wire inductance directly from its geometry and its environment A more simple approximation is given by following relation: cl εµ where c is capacitance per unit length, l inductance per unit length, ε electric permittivity and µ magnetic permeability of the surrounding dielectric Ex.: 0.5 µm technology a 0.4µm width Al wire routed on top of the field oxide (SiO ) has c 9aF/µm, l 0.47pH/µm 14

8 Example: Intel 0.5 micron Process 15 The Lumped C Model Conditions: resistive component of the wire is small consider only the capacitive component switching frequencies are in medium range The wire still represents an equipotential region and does not introduce any delay The distributed capacitance is lumped into a single capacitor The only impact on performance: loading effect of C lumped on the driving gate 16

9 The Lumped RC Model Metal wires of few mm length have a significant resistance and the equipotential assumption is no longer adequate! New model: Lumps the total resistance of the wire into a single resistor R Combines the global capacitance of the wire into a single capacitor C The estimated wire delay: τ RC This model is pessimistic and inaccurate for long interconnect wires! 17 The Elmore Delay Consider the following RC-tree network: the network has a single input node (s) all capacitors are between a node and the ground the network does not contain any resistive loops The shared path resistance R ik is the resistance shared among the paths from the source node s to the nodes k and i: R ik R, wherer j j [ path( s i) path( s k )] Ex.: R i4 R 1 + R 3 ; R i R 1 Assume that each node of the network is initially discharged and a step input is applied at t0 The Elmore delay at node i, for a network with N nodes, is given by: τ Di N k 1 C k R ik Ex.: τ Di R 1 C 1 + R 1 C + (R 1 + R 3 )C 3 + (R 1 + R 3 )C 4 + (R 1 + R 3 + R i )C i 18

10 The RC Chain Model RC chain -a special case of the RC-tree network: R V 1 in R R i-1 1 i-1 i N R i V N C 1 C C i-1 C i N i N τ C R C R Ex.: τ Di C 1 R 1 + C (R 1 + R ) C i (R R i ) DN i j i 1 j 1 i 1 i ii Assume that a wire of length L is modeled by N equal-length segments, each having R i rl/n, and C i cl/n (r, c are resistance and capacitance per unit length) τ DN L N N ( ) ( ) ( N + 1) rc + rc Nrc rcl N N + 1 RC N For N large, the RC chain model approach the distributed RC line model: (1) The delay of a wire is a quadratic function of its length τ RC DN () The delay of the RC chain model is 1/ of the delay predicted by the lumped RC model! rcl 19 The Distributed RC Line Model (1) L - total length of the wire r - resistance per unit length c - capacitance per unit length The voltage at node i is given by the following partial differential equation: Vi c L t ( V V ) ( V V ) i+ 1 i i i 1 r L For L -> 0, we obtain the diffusion equation: V rc t The diffusion equation is difficult to use for circuit analysis V x However, the distributed RC line can be approximated by a lumped RC chain network, and: rcl τ ( out ) V - the voltage at a particular point in the wire x - the distance between this point and the signal source 0

11 The Distributed RC Line Model () The step input waveform diffuses from the start to the end of the wire The waveform rapidly degrades: delay for long wires Voltage range Lumped RC network Distributed RC network 0 50%(tp) 0.69RC 0.38RC 0 63%(τ) RC 0.5RC 10% 90%(tr).RC 0.9RC 0 90%.3RC RC Step response of lumped and distributed RC networks: points of interests 1 Figures of Merit for RC Interconnect Criteria: (1) RC delays should be considered if interconnect delay, t p (RC), is comparable to driving gate delay, t p (gate). A critical length can be defined using the propagation table from slide 1: δ G L 0.38RC where L crit depends upon the sizing of the driving gate and the chosen interconnect material () A distributed RC model should be used if the rise (fall) time at the line input is smaller than the rise (fall) time of the line. Otherwise, a simple lumped C model suffices. tr < RC Example: Driving an RC line RwCw τ D RsCw + RsCw + 0.5rwc wl t 0.69R C R p s w w C w

12 Transmission Lines When the inductance of the wire dominates the delay behavior - transmission line effects! Model: a distributed RLC wire Signal propagate as a wave - alternatively transferring energy from electric to magnetic field r l r l r l r l V in x V out g c g c g c g c The wave propagation equation: v x v v rc + lc t t r,c,l - resistance, capacitance and inductance per unit length g ~ 0 - the leakage conductance The ideal wave propagation equation (for lossless transmission line, r0) : v x v lc t 1 ν v t ν 1 lc propagation speed along the line 3 Lossless Transmission Lines Parameters (1) Propagation speed: only a function of surrounding medium c 0 - speed of light in vacuum 1 1 c lc εµ ε µ ν 0 r r ε - electric permittivity of insulator µ - magnetic permeability of insulator ε r - relative permittivity with respect to vacuum µ r - relative permeability with respect to vacuum t flight L/v - the times it takes for the wave to propagate from one to the other end of the wire Dielectric constant and wave-propagation speed for various materials used in IC technology 4

13 Lossless Transmission Lines Parameters () Characteristic impedance: impedance presented by wire l Z0 lν c 1 cν 100 to 500Ω for typical wires The behavior of the transmission line is influenced by the termination of the line The termination how much of the wave is reflected upon arrival at the wire end ρ V V refl inc I I refl inc R R + ρ - Reflection coefficient Z Z R - the termination resistance R Z 0 ρ 0 R ρ 1 R 0 ρ Transmission Lines with Terminating Impedances Z s and Z L Consider the case: Z L, ρ 1 Z s V Source Z 0 V Dest V in Z L V Source (Z 0 /(Z 0 +Z s ))V in ρ s (Z s -Z 0 )/(Z s +Z 0 ) 6

14 Lattice Diagram t V. V V V... V Source L/ν V Dest V.7778 V V V V in 5V, R S 5Z 0, R L ρ s (Z s -Z 0 )/(Z s +Z 0 ) 0.66 ρ D 1 t 0... t flight V 1 S (Z 0 /(Z 0 +Z s ))V in 0.83V V 1 D V1 S + Vr,1 D ;Vr,1 D ρ D V1 S 0.83V 0.83V V V 1 D t t flight... t flight V S V1 S + Vr,1 D + Vr,1 S ; Vr,1 S ρ S Vr,1 D 0.55V V S.V V D V1 D + Vr,1 S + Vr, D ; Vr, D ρ D Vr,1 S 0.55V V D.77V... Conclusion: in order to avoid ringing or slow propagation delay the transmission line should be terminated both at the source (series termination) and at the destination (parallel termination) with a resistance equal to Z 0 7 Figures of Merit for RLC Interconnect Criteria: Rise (fall) time of input signal, t r, must be smaller than propagation delay through wire. Otherwise, a lumped model suffices. or t r t flight lw < Wire resistance R / damping factor ξ may not be too large, otherwise distributed RC model sufficient In conclusion: R rl < Z w tr lw lc < < r 0 rlw c ξ < 1 l l c lc l c Length (cm) High attenuation Inductance is important t r w lc < l l w < r 1. Large input rise time Transition time (ns) 1. &. l c 8

15 Scaling (1) VLSI integration depends on the smallest-size feature permitted by the technology The size of the transistors has to be as small as possible! The internal operating physics of the down-scaled MOS transistor changes First order scaling theory : Estimates the improvements that can be expected as technology is scaled Scaled MOS device is obtained by applying a dimensionless scaling factor α to: all dimensions (L, W, junction depth, oxide thickness, etc.) device voltages impurities concentration densities The characteristics of the scaled MOS device are similar to that of the original one A number of parameters such as voltage drop, line propagation delay, current density, contact resistance exhibit significant degradation with scaling! 9 Scaling () Influence of first-order scaling on MOS device Device Parameter Resultant Influence Parameter Scaling Factor Length; L 1/α Width; W 1/α Gate oxide thickness; t ox 1/α Junction depth; X j 1/α Substrate doping; N a or N d Supply voltage; V DD 1/α Electric field across gate oxide; E 1 Depletion layer thickness; d 1/α Parasitic capacitance; WL/t ox 1/α Gate delay; VC/I 1/α DC power dissipation; P s 1/α Dynamic power dissipation; P d 1/α Power speed product 1/α 3 Gate area 1/α Power density; VI/A 1 Current density; I/A α Transconductance; g m 1 α 30

16 Scaling (3) Interconnect layer scaling Parameter Scaling Factor Conductor line width; W 1/α Conductor line length; L 1/α Conductor line thickness; t 1/α Line cross-section; A 1/α Line resistance; r 1/α Line response time; rc 1 Normalized line response time 1/α Line voltage drop; V d 1 Normalized line voltage drop 1/α Current density; J 1/α Normalized contact voltage drop; V c /V 1/α The scaled line resistance is: ρ L / α r' αr t / α W / α The voltage drop along the scaled line is: ( I /α )( r) Ir ct V d ' α The scaled line response time is: τ / ( αr)( C ) rc ct s ' α For a constant chip size many of the signals paths do not scale down! Therefore: Voltage drops along the lines are larger by a factor of α than scaled line voltage drop The line response time is larger by a factor of α than scaled line response (see table) Problems: distribution and organization of clocking signals, electromigration, the increase of the wire capacitance (affects the gate delay) 31 Power Distribution Process with 1 Level of metal : V DD and ground (V SS ) are routed in interdigitated trees Crossunders are very difficult (low resistance interconnect) Power distribution is much easier for technologies with (or more) levels of metal Cautions: Parts of the chip that are likely to simultaneous transition are routed separately! Separate power pins might be used for the output driver! 3

17 Clock and Timing Circles (1) The clock synchronize machine operations and data transfer global control technique that provide the glue for system operation System level timing can be described using circular timing charts Ideal pseudo -phase clocking chart: φ 1 (t)φ (t) 0, t φ 1 1 during first half-period φ 1 during the last half-period time increases in a counter-clockwise direction one full rotation corresponds to a clock period T 33 Clock and Timing Circles () Overlapping pseudo -phase clocking chart: φ 1 (t)φ (t) 0, except during the transition times mutually-exclusive clock periods provide timing intervals for logical operations overlapped segments must be avoided transition times can be made small by proper clock generator design Clock skew is represented by rotating one of the clocks! φ 1 (t)φ (t) 1 defines the skew time, t s t s indicates the possibility of unwanted simultaneous bit transfer skew are caused by the clock driving circuit or by the distribution arrangement 34

18 Clock Generation Circuits (1) -phase clock generator with transmission gate delay M p1, M n1 inverter acts as the first driver for the chain Transmission gate (TG) is used as delay element to minimize clock skew TG is modeled as an equivalent resistance R TG and introduces a delay t D R TG C in t P - the propagation delay through an inverter Choosing t D ~ t P the delay between the two branches is the same Thus clocking skew can be controlled by adjusting the size of the TG transistors (β) R TG β n ( V V ) + β ( V V ) DD Tn 1 p DD Tp 35 Clock Generation Circuits () -phase clock generator with RS latch To insure proper operation of the circuit two items should be checked: t P through the inverter must be small compared to the clock period (CLK has time to enter the latch) the output capacitance in both branches should be equal for equal switching delays; but capacitances are sensitive to the layout and interconnect geometry! 36

19 Clock Drivers and Distribution Techniques (1) The clock driver must be able to handle large capacitive loads at the required clock frequency Clock skew originate mostly from: unbalanced loads at the driver unequal distribution line delays (RC) - see figure Distribution networks approaches: cascaded chain of inverting buffers that matches the clock generator to the distribution line balanced tree network with multiple fanouts symmetrical geometries (like H-tree) for the clock distribution lines 37 Clock Drivers and Distribution Techniques () Balanced tree network with multiple fanouts: identical drivers can be used within a given stage the drive requirements of the output circuits are reduced from the single inverter design since the fanout has been split into groups H-tree network: each clock distribution point O is at the same distance from the driver D, giving equal delay times 38

20 Input Protection Circuits (1) Excessive electrical charge on the gate of the MOS transistor can destroy the device! Protection circuits drain this excessive charge and avoid static burnout! C g C ox WL V E G 6 ox E V x cm BD ~ 7,5 10 / ox If E ox >E BD, the oxide insulating properties break down and charge is transported through the material - destruction of the device! The max gate voltage V Gmax is a relatively small number Static electricity during handling could easily reach a few kv 6 9 VG max EBD xox 7,5 10 V / cm V Protection circuits allow for alternate charge flow paths when the input voltage is too large Diode structures are very useful in this application because: have relatively low breakdown voltages which can be controlled reverse breakdown in a pn junction is non-destructive 39 Input Protection Circuits () Diode input protection circuit: D1...4 are reverse biased R reduces the voltage that reaches D3, D4 and increases the level of protection D1, D and D3, D4 undergo breakdown for positive or negative voltage sources Thick oxide MOSFET protection circuit: the transistor has the threshold voltage > V DD and is in cutoff during normal operation If V in > V T,f the transistor conducts providing a path to ground to drain off the excessive charge Input protection circuits introduce parasitic RC time constants into the network! 40

21 Static Gate Sizing (1) Problem - determine the values of S j for j,... which minimizes the total propagation delay through the inverter chain S j - sizing factor, S 1 1; S j >1 for j>1 β j - conduction factor, β 1 k (W/L) 1 ; β j S j β 1 C w - wiring contribution of gate 1 C i, C o - in/out capacitances of gate 1 C o,j S j C o - output capacitance from gate j C i,j S j C i - input capacitance to gate j C w,j S j C w - wiring capacitance of gate j The time delay through gate j is, t D,j : R t D, j o j i j w j j o j i + S,, + 1, + 1 j S + 1 j R ( C + C + C ) [ S C + S ( C C )] w 41 Static Gate Sizing () Suppose that there are N stages in the chain, the total time delay is given by: [ C + S ( C C )] N R S j o j+ 1 i + w TD j 1 S j TD To minimize T D we differentiate with respect to S j and look for zero slope points: 0 S j S j+ 1 S j This results in the recursion relation: for j,3,...n S S j j 1 If this to hold for arbitrary values of j, then: S j+1 S j K const The boundary conditions of the problem are: S 1 1, S N+1 C L /C i Forming the product: S S S S S S S S 3 4 N +1 We obtain the scaling ratio in the form: 1 3 N K N C C C L K C i L i 1/ N 4

22 Static Gate Sizing (3) Explicitly, the scaling factors are given by: S 1 1, S K, S 3 K... S N K N-1 The minimum delay is then: T D,min N j 1 [ + K( C + C )] NR[ C + K( C + C )] R C o i w o i w The equation K S j+1 /S j says that the minimum delay occurs when every stage has the same individual delay time t D The number of stages that optimize the delay is obtained by differentiating T D (replacing K with its N-dependent equation) with respect to N and setting the result to 0: If C o is small: with K N C C L i RC o + R ( C + C ) i w CL Ci 1 N ln 1 ( C / C )) L N i 0 C L N ln N is chosen the nearest integer for given values of C i and C L Ci CL N ln K ln Ci 1 N ln K N ln K 1 K e e the optimum scaling ratio equals e!!! 43 Off-Chip Driver Circuits Off-chip driver circuits are critical to the overall chip design Some important problems must be addressed: efficient buffer circuitry between internal and off-chip drivers minimization of transmission line effects fast switching static charge protection interface specific items, such as CMOS-TTL level converter, etc. An inverter circuit can be used as a basic off-chip driver Performance factors are : the transient switching times t LH and t HL transmission line effects 44

23 Double-Inverter Off-Chip Driver Circuit The simplest off-chip driver circuit: an inverter chain designed to handle a large capacitive load The sizes of M n and M p can be estimated using the high-to-low time constant τ n and the low-to-high time constant τ p : W L W L n τ n k' p τ p n k' C out ( V V ) p DD C Tn out ( V V ) DD Tp C out is large M n and M p are large! obtained using parallel connected transistors to aid in layout and parasitic control M n1 and M p1 can be sized using the previously presented sizing theory The actual values of the fall and rise time can be estimated from: ( ) V V V V ( ) Tp V Tn DD Tn t + ln 1 HL τ n DD VTp t LH τ p + ln 1 VDD VTn V 0 V V V DD Tp 0 where V 0 is the 10% voltage point 45 Example Consider a process characterized by the nominal values: k n 55[µA/V ] V T0n 0.9[V] k p 5[µA/V ] V T0p -0.75[V] and V DD 5[V] The requirements for off-chip driver circuits are t LH t HL 0[ns] with a maximum load of C out 50[pF] Using the previous equations we can compute the time constants τ n 6.45[ns] τ p 6.58[ns] the aspect ratios are: W L 35 n W L p 7 46

24 Tri-State Off-Chip Driver Circuit The input signal is split and individually control each output transistor The high-impedance state is obtained by driving both NMOS and PMOS output devices into cutoff Normal operation: Z 1 M p1 and M p off, M n on High-impedance state: Z 0 M p1 and M p on, M n off V p V DD, V n 0 the output transistors are in cutoff 47 Bidirectional Off-Chip Driver Circuit The tri-state section is a non-inverting buffer with an enable control E E 0 gives the high-z state 48

25 Packaging Technology (1) Package types 7 1. Bare die. Dual-In-line Package (DIP) 3. Pin Grid Array (PGA) Small-outline IC 5. Quad flat pack 4 6. Plastic Leaded Package (PLCC) 7. Leadless carrier Packaging Technology () Package has an important functionality in IC technology provides a means of bringing signal and supply wires in/out of the circuit removes the heat generated by the circuit protects the die against environmental conditions such as humidity provides mechanical support Meantime packaging technology has a tremendous impact on the performance up to 50% of the delay of a high-performance computer is due to packaging delays! Packages generate parasitic inductance and capacitance: Package Type Capacitance (pf) Inductance (nh) 68-pin plastic DIP pin ceramic DIP PGA Wire bond Solder bump

26 Packaging Technology (3) Example: parasitic effects of the bond-wire inductance A transient current is sourced/sunk from/into the supply rails to charge/discharge C L V in VDDext L i(t) V DDint V out C L L Inductive coupling between external (V DDext ) and internal (V DDint ) supply voltage (bonding wires) A changing current passing through an inductor generates a voltage drop: di v L dt v - the difference between V DDext and V DDint : affects the logic levels reduces the noise margin 51 Design techniques: Packaging Technology (4) Separate power pins for I/O pads and chip core Multiple power and ground pins Careful selection of the position of the power and ground pins on the package Adding decoupling capacitance on the board Increase the rise and fall times Use advanced packaging technologies + Board Wiring Bonding Wire SUPPLY - C d CHIP Decoupling Capacitor 5

27 Packaging Technology (5) Packaging Technology Requirements: Electrical: low parasitics (L, C, R) Mechanical: reliable and robust Thermal: efficient heat removal Economical: inexpensive Two interconnect levels: (1) Die-to-Package-Substrate () Package substrate to PCB 53 Packaging Technology (6) 1-a: Wire bonding Substrate Die Pad Lead Frame Wires must be attached serially Bonding wires have inferior electrical properties (L, C) Difficult to predict the exact value of parasitics (irregular) 54

28 1-b: Tape-automated bonding (TAB) Packaging Technology (7) Sprocket hole Film + Pattern Solder Bump Test pads Lead frame Die Substrate Polymer film The die is attached to a metal lead frame that is printed on a polymer film The connection between chip pads and polymer film wires is made using solder bumps Highly automated process Improve electrical performance (L ~ 0.5nH, C~0.3pF) 55 1-c: Flip-chip mounting Packaging Technology (8) Die Solder bumps Interconnect layers Substrate Flip the die upside-down and attach it directly to the substrate using solder bumps Superior electrical performance Pads can be placed at any position on the chip (not only on the die boundary) A possible solution for power and clock distribution problems 56

29 Packaging Technology (9) -a: Through-hole mounting mechanically reliable connections limits packaging density -b: Surface mounting increase package density: through holes are eliminated the lead pitch is reduced both sides of the board can be used the on-the-surface connection is weaker more expensive equipment needed testing on board is more complex 57 Multi-Chip-Modules (MCM) - Die-to-Board (avionics processor module - Rabaey96) Packaging Technology (10) Mount the die directly on the substrate increase the packaging density increase the performance reduce power consumption expensive technology 58

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