Digital Integrated Circuits EECS 312. Midterm exam 1 II. Homework 3 walkthrough. Review. Rent s rule. Inter-wire capacitance
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1 8 6 IM ES9 ipolar Fujitsu VP IM 9S NTT Fujitsu M-78 IM 9 D yber 5 Year of announcement IM RY5 IM RY7 Pulsar IM RY6 IM RY MOS Jayhawk(dual) T-Rex Mckinley IM GP Prescott Squadrons IM 9 Pentium IM 8 IM 8 pache Fujitsu M8 IM 7 Merced IM 6 IM Vacuum Pentium II(DSIP) Radio Receive for Mesh Maintenance - 6 m Typical urrent Draw sec Heartbeat beats per sample Sampling and Radio Transmission 9-5 m Low Power Sleep. -.5 m Heartbeat - m 6 8 Time (seconds) Digital Integrated ircuits EES dickrp/eecs/ Midterm exam I Teacher: Robert Dick Office: 7-G EES dickrp@eecs.umich.edu Phone: ellphone: HW engineers SW engineers GSI: urrent (m) Myung-hul Kim mckima@umich.edu Number of exams 5 Histogram of scores for Midterm Exam Power density (Watts/cm ) Score Robert Dick Digital Integrated ircuits Midterm exam II walkthrough verage: 8%. ommon problems Trouble interpreting layout: We can work on this a bit more in help sessions and class. Maybe not enough time understanding some of the questions. Question: Was there a lot of time pressure? Option: How about another short midterm after Thanksgiving break? dvantage: Less time pressure on final exam. dvantage: Less probability of a bad day messing up course score. Disadvantage: More stress and work. Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Review Rent s rule When are the advantages and disadvantages of fixed-voltage charging? When are the advantages and disadvantages of fixed-current charging? In what situation is each of the following models important? Ideal.. R. RL. What are di/dt effects? Under what circumstances do they cause the most trouble? T = ak p T: Number of terminals. a: verage number of terminals per block. k: Number of blocks within chip. p: Rent s exponent,, generally around.7. 5 Robert Dick Digital Integrated ircuits 7 Robert Dick Digital Integrated ircuits Fringe vs. parallel plate capacitance Inter-wire capacitance Plot of total for different gap ratios. 8 Robert Dick Digital Integrated ircuits 9 Robert Dick Digital Integrated ircuits
2 Impact of inter-wire capacitance Wire resistance R = ρl HW. onsider fixed-height, fixed-ρ square material, i.e., L W. R = k /W W, where k is a constant. Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Interconnect resistance Reducing resistance Material ρ (Ω m) 8 Silver.6 opper.7 Gold. luminum.7 Tungsten 5.5 Higher interconnect aspect ratios Material selection opper Silicides arbon nanotubes Structural changes More interconnect layers -D integration Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Silicides Resistances Material Sheet resistance (Ω/ ) n- or p-well diffusion,,5 n + or p + diffusion 5 5 silicided n + or p + diffusion 5 doped polysilicon 5 doped silicides polysilicon 5 luminum.5. Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits Multi-layer interconnect Side view of interconnect 6 Robert Dick Digital Integrated ircuits 7 Robert Dick Digital Integrated ircuits
3 Interconnect summary Delay modeling It is important to know which interconnect model to use in which situation. Ideal.. R. RL. di/dt effects are particularly important in power delivery networks. apacitive coupling complicates design. u and silicides can be used to reduce resistance. Single-node lumped model inaccurate. Full detailed accurate model intractable for manual analysis and slow for automated analysis. Elmore delay model permits rapid analysis with often adequate accuracy. 8 Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Elmore delay Special case: R chains Problem definition Goal: Determine τ for R path. Note: Source node is implicit. i : Self-capacitance of node i. R ii : Path resistance from source to node i. R ik : Shared resistance from source to both nodes i and k. N τ i = k R ik k= onsider π network. τ n = n i= i i j= R j. Use homogeneous discretization. N i= i = N τ = R nk k= = L N c L N(N + ) r N = rcl N + N What if N? τ rcl /. Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Underlying continuous physical model Power delivery network considerations cr δv δt = δ V δx IR drop. di/dt effects. Location of parasitic inductance. Methods to correct power delivery network non-idealities. Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Response to step function over time and space Simplifying assumptions Ignore wire R delay when wire delay does not much exceed that of the driving gate, i.e., tp,gate L crit.8rc Ignore wire R when rise time greater than R delay. Ignore for high-resistance wires: R >.. Ignore when time of flight is large compared to rise or fall time: t rise,fall <.5t flight. 5 Robert Dick Digital Integrated ircuits 6 Robert Dick Digital Integrated ircuits
4 Elmore delay summary Static MOS design styles and components Pick simplest model for intended purpose:, R, or RL. apacitive coupling complicates timing analysis. Transition direction impacts magnitude in simplified ground-cap model. Learn Elmore delay. It is a good first-order approximation of network delay. Logic gates DE Encoder Decoder 7 Robert Dick Digital Integrated ircuits 9 Robert Dick Digital Integrated ircuits Transistor sizing review MOS transmission gate (TG) Goal: equal τ for worst-case pull-up and pull-down paths. Observations dding duplicate parallel path halves resistance. dding duplicate series path doubles resistance. Doubling width halves resistance. onsider logic gate examples. Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Other TG diagram Multiplexer () definitions lso called selectors n inputs n control lines One output Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits functional table truth table I I I I 5 Robert Dick Digital Integrated ircuits 6 Robert Dick Digital Integrated ircuits
5 using logic gates using TGs I I I I I I I I 7 Robert Dick Digital Integrated ircuits 8 Robert Dick Digital Integrated ircuits Hierarchical implementation D : D I I I I I I 5 I 6 I 7 : S S : S S 8: : S 9 Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits lternative hierarchical implementation examples I I I I S S I I : m ux I I 5 S S S I 6 I 7 S = I + I Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits examples examples I I I I : m ux I I I I I I 5 I 6 8: m ux I 7 = I + I + I + I + = I + I + I + I I + I 5 + I 6 + I 7 Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits
6 properties example n : can implement any function of n variables n : can also be used Use remaining variable as an input to the F(,,) = (,,6,7) = Robert Dick Digital Integrated ircuits 6 Robert Dick Digital Integrated ircuits Truth table Lookup table implementation F 8: S S S F 7 Robert Dick Digital Integrated ircuits 8 Robert Dick Digital Integrated ircuits example Truth table Therefore, F(,,) = (,,6,7) = F = F = F = F = F F= 9 Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits Lookup table implementation summary S : S F Logic gate, transmission gate, and pass transistor design each have applications. -based design provides a good starting point for transmission gate and pass transistor based design. 5 Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits
7 Examples Upcoming topics Instead of flying through a bunch of slides, let s try examples. f (a) = a. f (a) = a f (a,b) = ab f (a,b) = ab (heck Figure 6- in J. Rabaey,. handrakasan, and. Nikolic. Digital Integrated ircuits: Design Perspective. Prentice-Hall, second edition,!) f (a,b,c) = ab + bc (try both ways). lternative logic design styles. Latches and flip-flops. Memories. 5 Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits assignment Special topic: tomic layer deposition 9 November, Tuesday: Read Section 6. in J. Rabaey,. handrakasan, and. Nikolic. Digital Integrated ircuits: Design Perspective. Prentice-Hall, second edition,. November, Thursday:. Katherine Dropiewski, Matt Jansen, and Olga Rouditchenko 56 Robert Dick Digital Integrated ircuits
Digital Integrated Circuits EECS 312. Review. Fringe vs. parallel plate capacitance. Rent s rule. Impact of inter-wire capacitance
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Digital Integrated Circuits EECS 312
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