! Dynamic Characteristics. " Delay


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1 EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic haracteristics 4 5 Review: Rise/Fall Times Review: MO Inverter Dynamic Performance! AALYI (OR IMULATIO: For a given MO inverter schematic and, estimate (or measure the propagation delays! DEIG: For given specs for the propagation delays and *, determine the MO inverter schematic METHOD:. Average urrent Model Δ HL OH 5% load I avg,hl I avg,hl. Differential Equation Model i out load out or τ PLH 3. st Order Relay Model i Assume in ideal
2 Review: Average urrent Model Review: Differential Equation Model Δ HL load OH 5% load I avg,hl I avg,hl τ PLH Δ LH I avg,lh 5% OL I avg,lh saturation linear t #t t #t 5% DD T n " % DD / " % $ ' out + DD $ ' # i Dn & DD T n # i Dn & out out DD Tn,sat load T n k n ( DD T n,lin load k n ( DD T n ln " ( % DD T n DD $ ' # DD & load T n k n ( DD T n + k n ( DD T n ln " ( % DD T n DD $ ' # DD & 8 T n k n ( DD T n ( DD T n + ln # ( DD T n &, + % (. * $ DD ' 9 Review: Design for Delays with More Realistic Review: onideal Input Waveform ideal in nonideal in out to ideal in out to nonideal in st Order R Delay Models st Order R Delay Model.69 bn + bp + int b! Equivalent circuits used for MO transistors " Ideal switch + effective O resistance + load capacitance " Define unit resistance, R u : effective O resistance of unit transistor with min length and WW u (usually min wih " Define R un and R up for nmo and pmo respectively " gb g and b sb for the unit n/pmo transistors 3
3 st Order R Delay Models.69 bn + bp + int b! Equivalent circuits used for MO transistors " Ideal switch + effective O resistance + load capacitance " Define unit resistance, R u : effective O resistance of unit transistor with min length and WW u (usually min wih " Define R un and R up for nmo and pmo respectively " gb g and b sb for the unit n/pmo transistors st Order R Delay Models! Equivalent circuits used for MO transistors " MO and pmo transistor at minimum gate length (L " apacitance directly proportional to gate wih (W # W* " onductance directly proportional to gate wih (W # G W*G " Resistance is inversely proportional to gate wih (W # R R/W " For scaled MO device with scale factors,, i.e. W n W un (W p W up " effective O resistance R un / ( R up / " capacitances, g (, g 4 Example Unit Transistors 5 st Order R Delay Model τ PLH st Order R Delay Model τ PLH (t DD ( e t/ (t DD ( e t/ tep ource t ( DD (t tep ource t ( DD (t 5% DD DD( e τ PLH /Rpload e τ PLH /Rpload ln τ PLH τ PLH ln( st Order R Delay Model τ PLH st Order R Delay Model  (t DD ( e t/ (t DD e t/ tep ource t ( DD (t 5% DD DD( e τ PLH /Rpload e τ PLH /Rpload ln τ PLH tep ource t ( DD DD (t 5% DD DDe / e / ln τ PLH ln(.69 ln(.69 ( # 5% OTE: τ ( # 63% 8 9 3
4 nmo st Order R Delay Model Equiv. nmo st Order R Delay Model Equiv. R un / R un / g O/ OFF Where W n W un, usually g O/ OFF Where W n W un, usually load DD k n ( DD T n.69r n load DD L un.69µ n ox W un ( DD T n pmo st Order R Delay Model Equiv. st Order Delay Model  s R up / g d O/ OFF τ PLH load DD k p ( DD T p.69r p load DD L up.69µ p ox W p ( DD T p Where W p W up, usually µ n /µ p A, n,κ p Y, where W n W unit >, R un W p W unit µ n / µ p R up / 3 st Order Delay Model  st Order Delay Model  s iff s iff A, n,κ p Y, Y n g A, n,κ p Y, Y n g where W n W unit >, R un n g where W n W unit >, R un n g W p W unit W p W unit µ n / µ p µ n / µ p R up / R up / 4 5 4
5 st Order Delay Model  st Order Delay Model  n g Y n g n g Y / n κ d n ng ( + ( + n g n g Y n g n g Y / n κ d n ng ( + ( + n g (+ ( + n g τ PLH 6 7 Review: MO Inverter Dynamic Performance Ring Oscillator! AALYI (OR IMULATIO: For a given MO inverter schematic and, estimate (or measure the propagation delays! DEIG: For given specs for the propagation delays and *, determine the MO inverter schematic METHOD:. Average urrent Model Δ HL OH 5% load I avg,hl I avg,hl. Differential Equation Model i out load out or τ PLH 3. st Order Relay Model i Assume in ideal Ring Oscillator Ring Oscillator YM I t 3 τ PLH3 τ PLH τ PLH 3 YM I > τ PLH 3 5
6 Ring Oscillator Interconnect Delay YM I > τ PLH τ p f T 6τ p nτ p τ p nf 3 Estimation of Interconnect Parasitics Digital ircuit Path Delay O O ritical Path?! Delays through logic blocks! etrelated delays " Fanout to other logic blocks " Interconnect (wiring Elmore Delay: Distributed etwork Elmore Delay! The delay from source s to node i " number of nodes in circuit
7 Elmore Delay: Distributed etwork! The delay from source s to node i " number of nodes in circuit k k ( [ path(s i path(s k] Elmore Delay: Distributed etwork! The delay from source s to node i " number of nodes in circuit k k ( [ path(s i path(s k]! Ex.? Elmore Delay: Distributed etwork Elmore Delay: Distributed etwork! The delay from source s to node i " number of nodes in circuit k k (R + (R + 3 (R + R (R + R 3 ( [ path(s 4 path(s k] + i (R + R 3 + R i OTE: τ D ( # 63%! The delay from source s to node i " number of nodes in circuit k k ( [ path(s 4 path(s k] R ( i +R 3 ( i +R i ( i τ p.69τ D ( # 5% 4 4 Interconnect Delay alculations Interconnect Delay alculations Lumped R Model for a Wire egment R ( R R ( 3 R 4 4 R ( 4 ( 4 5 R 6 R 7 ( 7 R ( 6 ( Lumped R Model for a Wire egment R ( R R ( 3 R 4 4 R ( 4 ( 4 5 R 6 R 7 ( 7 R ( 6 ( Lump total wire resistance of each wire segment into single between nodes in network.. Lump total capacitance into single node capacitor to GD. 3. Model R tree Topology: (a ingle input node ; (b All i between node i and GD; 4. Unique resistive path from source node to any node k (k. Elmore delay at nodes and 8? k k ( [ path(s i path(s k]
8 Interconnect Delay alculations Interconnect Delay alculations Lumped R Model for a Wire egment R ( R R ( 3 R 4 4 R ( 4 ( 4 5 R 6 R 7 ( 7 R ( 6 ( Lumped R Model for a Wire egment R ( R R ( 3 R 4 4 R ( 4 ( 4 5 R 6 R 7 ( 7 R ( 6 ( Elmore delay at nodes and 8? τ D R ( Elmore delay at nodes and 8? τ D R ( τ D8 R ( (R + R (R + R 6 + R (R + R 6 + R 7 + R Elmore Delay: pecial Ladder ase Elmore Delay: pecial Ladder ase! For each resistor i in path! For each resistor i in path " ompute R ii sum of all Rs upstream of i " ompute R ii sum of all Rs upstream of i τ D i i i j i R ii i τ D i i i j i R ii i *(R + *(R +R Elmore Delay: pecial Ladder ase ompare KL: etup! For each resistor i in path! Equations from KL? " ompute R ii sum of all Rs upstream of i τ D i i i j i R ii i *(R + *(R +R + R R R 3R 3ns R R
9 ompare KL: Math ompare KL: Math + R R + + R R R R " + R % $ ' R + R # & R R R + R R + R d + R! + R $ # & R + R " R % R! + R $! # & + R $ # & R! + R # " %" R % R "!! + R + R $ $ # # &+ R " " R & d + R R % % + (R + R + R d + R R + R d + R + R d $ & % 5 5 ompare KL: Math R R R + (R + R + R d + R R + 3R + R d ompare KL: Math R R R + (R + R + R d + R R + 3R + R d A(+ e αt A(+ e αt 3R αae αt + R α Ae αt 5 53 ompare KL: Math ompare KL: Math A(+ e αt A(+ e αt 3R αae αt + R α Ae αt t A (+ e αt 3R α e αt + R α e αt e αt 3R αe αt + R α e αt e αt ( 3Rα + R α 3Rα + R α (+ e αt 3Rα + R α α 3R ± 9(R 4(R 3R ± 5R 3± 5 (R (R R τ R.6R 3±
10 Elmore Delay: pecial Ladder ase! For each resistor i in path Interconnect Delay alculations R hain or Ladder etwork Wire Length L " ompute R ii sum of all Rs upstream of i R R R R 3 3 O τ D i i i j i R ii i *(R + *(R +R 3R 3ns 3 Let the R Ladder etwork be uniform, i.e. rl/ for all j and i cl/ for all i such that Interconnect Delay alculations Interconnect Delay alculations R hain or Ladder etwork Wire Length L R hain or Ladder etwork Wire Length L R R R R 3 3 O R R R R 3 3 O 3 3 Let the R Ladder etwork be uniform, i.e. rl/ for all j and i cl/ for all i such that τ D i! cl $ # & " % i! rl $ # & " % ( + j τ D rcl L (rc + rc + 3rc rc rcl + Let the R Ladder etwork be uniform, i.e. rl/ for all j and i cl/ for all i such that τ D i! cl $ # & " % i! rl $ # & " % ( + j τ D rcl L (rc + rc + 3rc rc rcl + 58 lim τ D rcl τ P.69τ D.35rcL 59 Interconnect Length RuleofThumb τ PLHInv.69 τ PWire.35rcL Interconnect Length RuleofThumb τ PLHInv.69 τ PWire.35rcL,, rl/ rl/ rl/ rl/ cl/ cl/ cl/ cl/,, rl/ rl/ rl/ rl/ cl/ cl/ cl/ cl/ τ PLHInv +τ Pwire rcL τ PLHInv +τ Pwire rcL Let the goal be for the layout to enable τ PLHInv τ PLHInv τ PLHInv >> τ Pwire 6 6
11 Interconnect Length RuleofThumb τ PLHInv.69 τ PWire.35rcL Interconnect Length RuleofThumb τ PLHInv.69 τ PWire.35rcL,, rl/ rl/ rl/ rl/ cl/ cl/ cl/ cl/,, rl/ rl/ rl/ rl/ cl/ cl/ cl/ cl/ τ PLHInv +τ Pwire rcL Let the goal be for the layout to enable τ PLHInv τ PLHInv τ PLHInv >> τ Pwire τ PLHInv +τ Pwire rcL Let the goal be for the layout to enable τ PLHInv τ PLHInv τ PLHInv >> τ Pwire.69 >>.35rcL L <<.69.35rc.69 >>.35rcL L <<.69.35rc L.69.35rc 6 63 Driving large load Driving Large Load standard MO logic on die I Buffer LOAD A DEIG TRATEGY: Make buffer (W/L n and (W/L p sufficiently large to drive LOAD with a specified τ P. How do you feel about this design strategy? Driving large load uperbuffer to Drive Large LOAD standard MO logic on die I Buffer LOAD A DEIG TRATEGY: Make buffer (W/L n and (W/L p sufficiently large to drive LOAD with a specified τ P. How do you feel about this design strategy? standard MO logic on die I DD LOAD LOA D PROBLEM: A minimum sized inverter drives a large load LOAD, leading to excessive delay, even with a large buffer OLUTIO: Insert (large inverter W/L. stages in cascade with increasing W/L between I and load LOAD. The total delay through smaller stages will be less than the delay through a single large stage driving LOAD. What happens to in as (W/L n and (W/L p sufficiently large? What is the impact on the standard MO logic on the die? DD 3 LOAD 66 67
12 uperbuffer to Drive Large LOAD I tage uperbuffer to Drive Large LOAD I tage LOAD LOAD a > stage scale factor > OTE for MO I: bn + bp g gbn bp W ni a i W n, L ni L n and W pi a i W p, L pi L p for i,,,..., a > stage scale factor > OTE for MO I: bn + bp g gbn bp W ni a i W n, L ni L n and W pi a i W p, L pi L p for i,,,..., tage load capacitances i are also scaled by a i a i a i ( + a g for i,,,.., when i : a a ( + a g > let LOAD a (a g a + g 68 LOAD / g a + > ln( LOAD g ln a is rounded up to nearest integer value. 69 uperbuffer to Drive Large LOAD uperbuffer to Drive Large LOAD LOAD LOAD LOAD LOAD For tage: τ p τ W + a g ( W τ p τ + a g OTE: ALL inverters tage through tage have the same gate delay τ p +τ PLH Γ W Let τ gate delay for I (with a with load For tage: For tage: ( / a τ p aw a + a g τ ( W ( / a τ p a W a + a + g τ ( W τ p τ d + a g τ p τ p τ d + a g τ p τ p W load + a g τ p τ d + a g For tage: τ ( W 7 7 uperbuffer to Drive Large LOAD uperbuffer to Drive Large LOAD For tage: For tage: For tage: τ p τ W + a g ( W ( / a τ p aw a + a g τ ( W ( / a τ p a W a + a + g τ ( W τ total ( +τ p ( +τ d + a g LOAD LOAD τ p τ + a g τ p τ d + a g τ p τ p τ d + a g τ p hoose and a to minimize τ total 7 τ total ( +τ p ( +τ + a g ln( LOAD g ln a TO MIIMIZE τ total : dτ total da τ ln LOAD g τ total ln( LOAD g τ d + a g ln a W ni a i W n # / a d + a g + & % g ( $ %( ln a ln a '( g / a + a g + ( ln a ln a a opt #$ ln a opt & ' g W pi a i W p 73
13 uperbuffer to Drive Large LOAD τ total ( +τ p ( +τ + a g ln( LOAD g ln a TO MIIMIZE τ total : dτ total da τ ln LOAD g τ total ln( LOAD g τ d + a g ln a W ni a i W n # / a d + a g + & % g ( $ %( ln a ln a '( g / a + a g + ( ln a ln a a opt #$ ln a opt & ' g W pi a i W p EXAMPLE: Design a Buffer using a scaled cascade of inverters to achieve minimum total delay t total when LOAD g. onsider the case where g. g > plot a opt as function of / g : a opt 4.35 > ln a opt.47 e uperbuffer to Drive Large LOAD a opt 4.35 / g ln( LOAD g.3 3 ln a a is only an academic special case. opt [ln a opt ] g Idea Admin! Propogation Delay " st Order Model! Interconnect Delay " Elmore Delay to Approx/Optimize Delay " Ruleofthumb: Design wire delay << stage delay! Driving large loads " Use scaled up buffers with optimal stages and scale factor ( and a! HW 5 due Thursday, 3/ " tart it if you haven t already " A lot of adence
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