Semiconductor memories

Transcription

1 Semiconductor memories

2 Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations?

3 Semiconductor Memories RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM

4 Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line M.2 K Sense Amplifiers / Drivers Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits)

5 Architecture: example 256 cells = 32 bytes 16 columns L=5 L-K 16 rows 2 4 M = 8 K = 1 L-K=4 M K 2 bytes 8 x 2 1

6 Blocks ( 1Mbit) Row Address Column Address Block Address Control Circuitry Block Selector Global Amplifier/Driver I/O Global Data Bus Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

7 Architecture: example 256 cells = 32 bytes = 8 blocks (32 bits) 4 columns 8 rows.. Block 0 Block 1 Block 7

8 Area occupation INTEL Kx1bit SRAM 1972

9 Area occupation Micron 1 Gbit DRAM Today

10 Write/read cycles Read Cycle READ Read Access Read Access Write Cycle WRITE Data Valid Write Access DATA Data Written

11 Semiconductor Memories Write cycle Read cycle

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13 Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

14 6-transistor CMOS SRAM Cell WL M2 M4 M5 Q Q M6 M2 M4 Q Q M1 M3 M6 M1 M3 M8 S M5 M7 R SR Flip-Flop

15 CMOS SRAM Analysis (Read) WL precharge sensing M4 WL Q = 0 M6 M5 Q = 1 M1 V DD /2 /2 C bit C bit /2 Out 0V k n M V V DD DD V 2 2 Tn V 2 = k 2 n M1 V Tn DD 2 8 Differential sense amplifier (W/L) n,m5 10 (W/L) n,m1 (supercedes read constraint) Out pin

16 CMOS SRAM Analysis (Read)

17 CMOS SRAM Analysis (Read) WL M4 M5 Q = 0 Q = 1 M6 M1 V DD /2 /2 C bit C bit k n M V V DD DD V 2 2 Tn V 2 = k 2 n M1 V Tn DD 2 8 (W/L) n,m5 10 (W/L) n,m1 (supercedes read constraint)

18 CMOS SRAM Analysis (Write) WL M4 M5 Q = 0 Q = 1 M6 M1 = 1 = 0 k n M6 V Tn V 2 DD V DD = k p M4 2 8 V Tp V DD 8 (W/L) n,m (W/L) p,m4 k n M V V DD DD V Tn k 2 2 n M1 V Tn = (W/L) n,m5 10 (W/L) n,m1 in ( =0)

19 CMOS SRAM Analysis (Write) WL M4 M5 Q = 0 Q = 1 M6 M1 = 1 = 0 k n M6 V Tn V 2 DD V DD = k p M4 2 8 V Tp V DD 8 (W/L) n,m (W/L) p,m4 k n M V V DD DD V Tn k 2 2 n M1 V Tn = (W/L) n,m5 10 (W/L) n,m1

20 6 transistor SRAM : features 6 transistors cell (large number!) nmos and PMOS in the cell wells 5 lines :,, WL, VDD, GND Critical read driven by small cell transistors increase access time

21 Resistance-load SRAM Cell WL M3 Q M1 R L M2 Q R L M4 Reduced cell size : No well Possible vertical integration Static power dissipation Very high value of R L not suitable for embedded Static power dissipation -- Want R L large Bit lines precharged to to address t p problem

22 1-Transistor DRAM Cell WL M1 x C S WL X GND Write "1" Read "1" V T C C S 30fF /2 sensing /2 C /C S Write: C S is charged or discharged by asserting WL and. Read: Charge redistribution takes places between bit line and storage capacitance C S V = V V PRE = V BIT V PRE C S + C Voltage swing is small; typically around 250 mv.

23 DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than.

24 1-T DRAM Cell Capacitor Metal word line poly SiO 2 M1 word line n + n + Field Oxide poly Inversion layer induced by plate bias (a) Cross-section Diffused bit line Polysilicon gate Polysilicon plate (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area

25 Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Storage electrode Isolation Storage Node Poly 2nd Field Oxide Si Substrate Trench Cell Stacked-capacitor Cell

26 Periphery D e c o d e rs S e n s e A m p lifie rs In p u t/o u tp u t B u ffe rs C o n tro l / T im in g C ir c u itry

27 Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

28 Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 1 WL 0 WL 0 A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder Propagation delay is primary concern

29 4 input pass-transistor based column decoder A 0 A 1 2 input NOR decoder S 0 S 1 S 2 S 3 D dvantage: speed (t pd does not add to overall memory access time) only 1 extra transistor in signal path sadvantage: large transistor count

30 4-to-1 tree based column decoder A 0 A 0 A 1 A 1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches

31 Sense Amplifiers t p = C V I av make V as small as possible large small Idea: Use Sense Amplifer small transition s.a. input output

32 Differential Sensing - SRAM PC y M3 M4 y EQ x M1 M2 SE M5 x x SE x WL i (b) Doubled-ended Current Mirror Amplifier SRAM cell i Diff. x Sense x Amp y y D D x y SE y x (a) SRAM sensing scheme. (c) Cross-Coupled Amplifier

33 Differential Sensing - SRAM P WL S

34 Latch-Based Sense Amplifier EQ SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.

35 Open bitline architecture EQ R L 1 L 0 R 0 R 1 SE L L R C S... C S C S SE... C S C S C S dummy cell dummy cell

36 DRAM Read Process with Dummy Cell 6.0 V (Volt) V (Volt) t (nsec) (a) reading a zero V (Volt) WL 3.0 SE 2.0 EQ (c) control signals t (nsec) (b) reading a one

37 Open Bit-line Architecture Cross Coupling EQ WL 1 WL 0 WL D WL D WL 0 WL 1 C W C W C C C C Sense Amplifier C C C C

38 Alpha-particles -particle WL n + SiO 2 1 particle ~ 1 million carriers

39 Yield Yield curves at different stages of process maturity (from [Veendrick92])

40 Redundancy Redundant columns Redundant rows Memory Array Row Address Row Decoder : Fuse Bank Column Decoder Column Address

41 Redundancy and Error Correction