SEMICONDUCTOR MEMORIES
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1 SEMICONDUCTOR MEMORIES
2 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
3 Memory Architecture: Decoders M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N
4 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line M.2 K Sense Amplifiers / Drivers Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits)
5 Hierarchical Memory Architecture Row Address Column Address Block Address Control Circuitry Block Selector Global Amplifier/Driver I/O Global Data Bus Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings
6 Memory Timing: Definitions Read Cycle READ Read Access Read Access Write Cycle WRITE Data Valid Write Access DATA Data Written
7 Non Volatile Memory Masked ROM Floating gate based (NVRWM)
8 MOS NOR ROM V DD Pull-up devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3]
9 MOS NOR ROM Layout Metal1 on top of diffusion WL[0] WL[1] Basic cell 10 λ x 7 λ GND (diffusion) Polysilicon Metal1 WL[2] 2 λ WL[3] Only 1 layer (contact mask) is used to program memory array Programming of the memory can be delayed to one of last process steps
10 MOS NOR ROM Layout BL[0] BL[1] BL[2] BL[3] Threshold raising implant WL[0] Basic Cell 8.5 λ x 7 λ WL[1] GND (diffusion) Metal1 over diffusion Polysilicon WL[2] WL[3] Threshold raising implants disable transistors
11 MOS NAND ROM BL[0] BL[1] BL[2] BL[3] V DD Pull-up devices WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row
12 MOS NAND ROM Layout Diffusion Basic cell 5 λ x 6 λ Polysilicon Threshold lowering implant No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM
13 Programmable Logic Array Product Terms AND PLANE x 0 x 1 x 2 OR PLANE f 0 f 1 x 0 x 1 x 2
14 Pseudo-Static PLA GND GND GND GND V DD GND GND GND V DD x 0 x 0 x 1 x 1 x 2 x 2 f 0 f 1 AND-PLANE OR-PLANE
15 Dynamic PLA φ AND GND V DD φ OR V DD φ AND x 0 x 0 x 1 x 1 x 2 x 2 f 0 f 1 GND φ OR AND-PLANE OR-PLANE
16 PLA Layout And-Plane VDD x0 x0 x1 x1 x2 x2 Pull-up devices Elettronica D A.A Memory Or-Plane φ GND f0 f1 Pull-up devices
17 PLA versus ROM Programmable Logic Array structured approach to random logic two level logic implementation NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM! Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA s has drastically reduced 1. slow 2. better software techniques (mutli-level logic synthesis)
18 NVRWM: Floating-gate transistor Source Floating gate Gate Drain D t ox G t ox n + Substrate p n + S (a) Device cross-section (b) Schematic symbol
19 Floating gate Transistor Q = 0 CV V V 1 G1 G2 G1 + C (V 1 2 C2 = C + C C = (1+ C G1 Mosfet ON if V )V -V G2 G1 G2 ) = 0 V > V g1 C 1 V G2 > (1+ )V T = C2 T V ' T
20 Floating gate Transistor Q < 0 C V V V 1 G1 G2 G1 + C 1 2 C = (1+ C Mosfet ON if (V C2 = C + C G1 V )V -V G2 G1 G2 + C 1 Q - C ) = Q 2 V > V g1 Q + C 2 T C1 Q "' VG 2 > (1+ )V T - = VT ( > V C C 2 2 ' T )
21 Floating-Gate Transistor Programming 20 V 0 V 5 V 20 V 10 V 5 V 5 V 0 V 2.5 V 5 V S D S D S D Avalanche injection. Removing programming voltage leaves charge trapped. Programming results in higher V T.
22 EEPROM MEMORY CELL Source Floating gate Gate Drain I n nm Substrate p 10 nm (a) Flotox transistor n + 10 V 10 V V GD (b) Fowler-Nordheim I-V characteristic BL WL V DD (c) EEPROM cell during a read operation
23 Flash Memory Cell Control gate Floating gate erasure Thin tunneling oxide n + source programming p-substrate n + drain
24 Cross-sections of NVM cells Flash Courtesy Intel EPROM
25 Characteristics of State-of-the-art NVM
26 Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
27 6-transistor CMOS SRAM Cell WL V DD M2 M4 M5 Q Q M6 M1 M3 BL BL
28 6T-SRAM Layout V DD M2 M4 Q Q M1 M3 M5 M6 GND WL BL BL
29 Resistance-load SRAM Cell WL V DD R L R L M3 Q Q M4 BL M1 M2 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem
30 Differential Sensing - SRAM V DD V DD V DD PC V DD y M3 M4 y BL EQ BL x M1 M2 SE M5 x x SE x WL i (b) Doubled-ended Current Mirror Amplifier SRAM cell i V DD Diff. x Sense x Amp y y D D x y SE y x (a) SRAM sensing scheme. (c) Cross-Coupled Amplifier
31 1-Transistor DRAM Cell BL WL WL Write "1" Read "1" M1 C S X GND V DD V T C BL BL V DD /2 V DD sensing V DD/2 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance C S V = V BL V PRE = ( V BIT V PRE ) C S + C BL Voltage swing is small; typically around 250 mv.
32 1-T DRAM Cell Capacitor Metal word line poly SiO 2 M1 word line n + n + Field Oxide poly Inversion layer induced by plate bias (a) Cross-section Diffused bit line Polysilicon gate Polysilicon plate (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area
33 DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD.
34 SEM of poly-diffusion capacitor 1T-DRAM
35 Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Storage electrode Isolation Storage Node Poly 2nd Field Oxide Si Substrate Trench Cell Stacked-capacitor Cell
36 Memory Architecture Dummy Cell EQ WL 1 WL 0 WL D WL D WL 0 WL 1 C WBL C WBL BL BL C BL C C C Sense Amplifier C C C C BL
37 Sense Amplifier BL V DD EQ BL SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
38 Architecture R SE V DD EQ L 1 L 0 R 0 R 1 L BLL BLR C S... C S C S SE... C S C S C S dummy cell dummy cell
39 DRAM Read Process with Dummy Cell 6.0 V (Volt) V (Volt) t (nsec) (a) reading a zero BL BL BL BL V (Volt) WL 3.0 SE 2.0 EQ (c) control signals t (nsec) (b) reading a one
40 Folded-Bitline Architecture WL 1 WL 1 WL 0 WL 0 WL D WL D C WBL BL C BL x y... C C C C C C EQ Sense Amplifier BL C BL x y C WBL
41 Transposed-Bitline Architecture BL BL BL BL" C cross (a) Straightforward bitline routing. SA BL BL BL BL" C cross SA (b) Transposed bitline architecture.
42 Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
43 Dynamic Decoders Precharge devices GND GND V DD WL 3 V DD WL 3 WL 2 V DD WL 2 WL 1 V DD WL 1 WL 0 WL 0 V DD φ A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 φ Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder Propagation delay is primary concern
44 A NAND decoder using 2-input predecoders WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 Splitting decoder into two or more logic layers produces a faster and cheaper implementation
45 4 input pass-transistor based column decoder BL 0 BL 1 BL 2 BL 3 A 0 A 1 2 input NOR decoder S 0 S 1 S 2 S 3 dvantage: speed (t pd does not add to overall memory access time) only 1 extra transistor in signal path sadvantage: large transistor count D
46 4-to-1 tree based column decoder BL 0 BL 1 BL 2 BL 3 A 0 A 0 A 1 A 1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
47 Reliability and Yield
48 Yield Yield curves at different stages of process maturity (from [Veendrick92])
49 Redundancy Redundant columns Redundant rows Memory Array Row Address Row Decoder : Fuse Bank Column Decoder Column Address
50 Redundancy and Error Correction
51 Semiconductor Memory Trends Memory Size as a function of time: x 4 every three years
52 Semiconductor Memory Trends Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation
53 Semiconductor Memory Trends Technology feature size for different SRAM generations
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