Magnetic core memory (1951) cm 2 ( bit)

Transcription

1 Magnetic core memory (1951) cm 2 ( bit)

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3 Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register

4 Memory Timing: Definitions Read cycle READ Read access Read access Write cycle WRITE Data valid Write access DATA Data written

5 N w o r d s D e c o d e r Memory Architecture: Decoders M bits M bits S 0 S 1 S 2 Word 0 Word 1 Word 2 Storage cell A 0 A 1 S 0 Word 0 Word 1 Word 2 Storage cell S N 2 2 Word N2 2 A K 2 1 Word N2 2 S N 2 1 Word N2 1 K = log 2 N Word N2 1 Input-Output (M bits) Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Decoder reduces the number of select signals K = log 2 N

6 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L 2 K Bit line Storage cell A K A K1 1 A L 2 1 Row Decoder Word line Sense amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K2 1 Column decoder Selects appropriate word Input-Output (M bits)

7 Memory Timing: Approaches Address bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operation RAS-CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

8 Read-Only Memory Cells BL BL BL 1 WL WL V DD WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2

9 MOS NAND ROM V DD Pull-up devices BL[0] BL[1] BL[2] BL[3] WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row

10 Non-Volatile Memories The Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol

11 Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V 2 5 V 0 V V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T.

12 A Programmable-Threshold Transistor I D 0 -state 1 -state ON DV T OFF V WL V GS

13 FLOTOX EEPROM FLOating gate Tunneling OXide Floating gate Source Gate Drain I nm n 1 Substrate p n 1 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic

14 Cross-sections of NVM cells Flash Courtesy Intel EPROM

15 Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

16 6-transistor CMOS SRAM Cell WL V DD M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL

17 Resistance-load SRAM Cell V DD WL R L R L M 3 Q Q M 4 BL M 1 M 2 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem

18 SRAM Characteristics

19 Esempio di organizzazione di una cella di memoria statica dato in selezione colonna S Q selezione riga R pass-gate (three state) dato out abilitazione scrittura abilitazione lettura

20 Esempio di organizzazione di una cella di memoria statica dato in dato in dato out selezione riga dato out dato in dato out abilitazione scrittura selezione colonna abilitazione lettura

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26 3-Transistor DRAM Cell BL1 BL2 WWL RWL WWL M 3 RWL M 1 X M 2 X V DD - V T C S BL 1 V DD BL 2 V DD - V T V No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn

27 1-Transistor DRAM Cell WL BL WL Write 1 Read 1 M 1 X GND V DD 2 V T C S V DD BL V DD /2 V sensing DD /2 C BL Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mv.

28 DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost.

29 1-T DRAM Cell Metal word line Poly SiO 2 n + n + Field Oxide Poly Inversion layer induced by plate bias Cross-section Expensive in Area

30 Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Trench Cell Stacked-capacitor Cell

31 Periphery Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

32 DRAM Timing

33 Reliability and Yield

34 R o w D e c o d e r Redundancy Redundant columns Redundant rows Memory Array Row Address Fuse : Bank Column Decoder Column Address

35 Error-Correcting Codes with e.g. B3 Wrong 1 1 = 3 0

36 Redundancy and Error Correction

37 125mm 2 1Gbit NAND Flash Memory 10.7mm Charge pump 2kB Page buffer & cache 32 word lines x 1024 blocks bit lines 11.7mm From [Nakamura02]

38 125mm 2 1Gbit NAND Flash Memory Technology 0.13µm p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al Cell size 0.077µm2 Chip size 125.2mm2 Organization 2112 x 8b 8b x page x 1k 1k block Power supply 2.7V-3.6V Cycle time 50ns Read time 25µs Program time 200µs // page Erase time 2ms // block From [Nakamura02]