CMSC 313 Lecture 25 Registers Memory Organization DRAM
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1 CMSC 33 Lecture 25 Registers Memory Organization DRAM UMBC, CMSC33, Richard Chang
2 A-75 Four-Bit Register Appendix A: Digital Logic Makes use of tri-state buffers so that multiple registers can gang their outputs to common output lines. D 3 D 2 D D Write (WR) CLK D Q D Q D Q D Q Enable (EN) WR D 3 D 2 D D Q 3 Q 2 Q Q EN Q 3 Q 2 Q Q 999 M. Murdocca and V. Heuring
3 A-76 Appendix A: Digital Logic Left-Right Shift c Register with c Shift left output Shift right input D 3 D 2 D D Shift right input Parallel Read and c Write c CLK Enable (EN) D Q D Q D Q D Q Shift right output Q 3 Q 2 Q Q Control Function c c No change Shift left Shift right Parallel load Shift right input Shift left output c c D 3 D 2 D D Q 3 Q 2 Q Q Shift right output Shift right input 999 M. Murdocca and V. Heuring
4 3-5 A Serial Multiplier Chapter 3: Arithmetic Multiplicand (M) m 3 m 2 m m 4 Add 4 Bit Adder 4 Shift Right Shift and Add Control Logic q C a 3 a 2 a a q 3 q 2 q q A Register 4 Multiplier (Q) 999 M. Murdocca and V. Heuring
5 3-6 Example of Multiplication Using Serial Multiplier Chapter 3: Arithmetic Multiplicand (M): C A Q Initial values Add M to A Shift Add M to A Shift Shift (no add) Add M to A Shift Product 999 M. Murdocca and V. Heuring
6 7-4 Chapter 7: Memory Functional Behavior of a RAM Cell Read D Q CLK Select Data In/Out 999 M. Murdocca and V. Heuring
7 7-5 Chapter 7: Memory Simplified RAM Chip Pinout WR Memory Chip A -A m- D -D w- CS 999 M. Murdocca and V. Heuring
8 7-6 D 3D2 D D Chapter 7: Memory A Four-Word Memory with Four Bits per Word in a 2D Organization A A 2-to-4 decoder Chip Select (CS) WR WR CS Word WR CS Word WR CS Word 2 WR CS Word 3 Q 3Q2 Q Q 999 M. Murdocca and V. Heuring
9 7-7 Chapter 7: Memory A Simplified Representation of the Four-Word by Four-Bit RAM D 3 D 2 D D WR A A 4 4 RAM CS Q 3 Q 2 Q Q 999 M. Murdocca and V. Heuring
10 7-8 Chapter 7: Memory 2-/2D Organization of a 64-Word by One-Bit RAM Read D Q A A A 2 Row Decoder Read/Write Control Row Select CLK A 3 A 4 A 5 Column Decoder (MUX/DEMUX) Data Two bits wide: One bit for data and one bit for select. Data In/Out One Stored Bit Column Select 999 M. Murdocca and V. Heuring
11 A-33 Appendix A: Digital Logic Decoder Enable = Enable = D A D B Enable D 2 D 3 A B D D D 2 D 3 A B D D D 2 D 3 D = A B D = A B D 2 = A B D3 = A B 999 M. Murdocca and V. Heuring
12 7-9 Chapter 7: Memory Two Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by Eight-Bit RAM CS WR D 7 D 6 D 5 D 4 D 3 D 2 D D A A 4 4 RAM 4 4 RAM Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q Q 999 M. Murdocca and V. Heuring
13 7- Chapter 7: Memory Two Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAM D 3 D 2 D D WR A A 4 4 RAM CS A 2 -to-2 decoder CS 4 4 RAM CS Q 3 Q 2 Q Q 999 M. Murdocca and V. Heuring
14 7- Single-In-Line Memory Module Chapter 7: Memory Adapted from(texas Instruments, MOS Memory: Commercial and Military Specifications Data Book, Texas Instruments, Literature Response Center, P.O. Box 72228, Denver, Colorado, 99.) A-A9 CAS DQ-DQ8 NC RAS V cc V ss W PIN NOMENCLATURE Address Inputs Column-Address Strobe Data In/Data Out No Connection Row-Address Strobe 5-V Supply Ground Write Enable Vcc CAS DQ A A DQ2 A2 A3 Vss DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 NC DQ6 W Vss DQ7 NC DQ8 NC RAS NC NC Vcc M. Murdocca and V. Heuring
15 Types of Random Access Memory Static RAM (SRAM) Each bit is stored in a type of flip-flop Typically takes four or six transistors per bit Faster, but takes up more space in a chip Retains information as long as power is supplied Not to be confused with flash memory in digital cameras (EEPROMs) Dynamic RAM (DRAM) Each bit is stored in a capacitor Uses one capacitor and one transistor per bit Slower, but takes up less space in a chip Must be refreshed periodically (milliseconds), since the capacitor leaks UMBC, CMSC33, Richard Chang <chang@umbc.edu>
16 A DRAM memory cell Word Line DRAM Capacitor GND Bit Line Word line selects cell for reading or writing To write, the bit line is charged with logic or To read, sensitive amplifier circuits detect small changes in bit line. Reading discharges the capacitor. UMBC, CMSC33, Richard Chang
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18 DRAM Read Cycle. Row address placed on the address bus. 2. Row Address Strobe (RAS) is asserted, allowing the row address to latch. 3. Row address decoder selects proper row. 4. Write Enable (WE) disabled. 5. Column address placed on the address bus. 6. Column Address Strobe (CAS) is activated, allowing the column address to latch. 7. Once the CAS signal has stabilized, sensing amplifiers places data from the selected row & column on data bus. 8. RAS and CAS deactivated. Cycle begins again. UMBC, CMSC33, Richard Chang
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20 DRAM DRAM is asynchronous, ignores system bus clock. trac = Row Access Time = delay from RAS assertion until data is ready tcac = Column Access Time = delay from CAS assertion until data is ready DRAM access is sloooooow Each memory access must wait for time it takes to activate and deactivate RAS. Fast Page Mode (FPM) DRAM allows successive reads from the same row without deactivating RAS. Extended Data Out (EDO) DRAM overlaps CAS assertion and data reads. UMBC, CMSC33, Richard Chang <chang@umbc.edu>
21
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23 Synchronous DRAM (SDRAM) Uses system bus clock. Current models run at 433MHz (still much slower than CPU). Burst mode allows fast successive reads from the same row. (Good way to read in a cache line!) Double Data Rate (DDR) SDRAM provides data on the positive and negative edges of the clock. UMBC, CMSC33, Richard Chang <chang@umbc.edu>
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25 Next Time Cache Memory UMBC, CMSC33, Richard Chang
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