Single Event Effects: SRAM

Transcription

1 Scuola Nazionale di Legnaro 29/3/2007 Single Event Effects: SRAM Alessandro Paccagnella Dipartimento di Ingegneria dell Informazione Università di Padova

2 OUTLINE Introduction The first SEE observations on RAMs : DRAM Single Event impact on CMOS inverter and SRAM cell: flipping the bit SRAM SEU: mapping cross section critical charge Scaling issues in SRAM SEU Non-volatile memories Conclusions

3 Introduction Why SEE s on SRAM s? The Static Random Access Memory (SRAM) is a benchmark to evaluate the SEE sensitivity SRAM is the easiest latch to be fabricated in standard CMOS technology (DRAM or FLASH need dedicated process steps) SRAM s are widely used in all logic circuits SRAM cell size scales with Moore s law SRAM cells can be simulated in detail Memories are easier to test than logic (such as DSP) SEE measurements are straightforward even on commercial parts

4 Early reports of SEE s in memories SEE s in memories typically refer to the loss of information from a memory cell caused by a single ionizing particle: Single Event Upset (SEU) In a Flip-Flop (Latch) the information corruption is associated to the bit flip: 0 1 or 1 0 and is reversible: the right bit can be rewritten Memory arrays are organized in words and more than one SEU may affect a single word: Single Bit Upset (SBU) Multiple Bit Upset (MBU) Soft Error Rate (SER) First report on memories: a bipolar flip-flop circuit (Binder et al., 1975) affected by cosmic rays in satellites RAMs may be affected also by permanent SE effects (i.e., stuck bits)

5 SEU in early DRAMs: no effect on 0 The DRAM case: SEU s observed at sea level in Intel 16K DRAM s (1979) generated by alpha particles produced by radioactive contaminants T.C. May and M.H. Woods, IEEE-TED26, 1979

6 SEU in early DRAMs: 1 flips T.C. May and M.H. Woods, IEEE-TED26, 1979

7 Critical Charge in DRAM s Usually the Critical Charge is defined as Q crit = V c. C s, where C s is storage capacitance Critical voltage, V c, is typically half the power supply voltage In SRAM cells things may be substantially different

8 6-Transistor (6T) CMOS SRAM Cell WL V DD M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL J.Rabey, Digital Integrated Circuits, Prentice Hall, 1996

9 SE in CMOS inverter: OUT = 1 V SS in out V DD PMOS N+ N+ P substrate P. Fouillat, EWRHE 2004 A current is observed ION The output node out is discharged A current is injected by the PMOSFET into the out node to restore the initial charge and logic value

10 SE in CMOS inverter: OUT = 0 V SS in out V DD PMOS N+ N+ P substrate P. Fouillat, EWRHE 2004 No current is observed ION Only reversed biased junctions of off-state MOSFET drains may effectively collect charge and affect the out node voltage

11 SEU in SRAM cell ION V DD V SS V DD V SS Upsetting a memory cell P. Fouillat, EWRHE 2004

12 6T-SRAM Layout CMOS INVERTERS: M2 M4 V DD PMOSFETs Q Q Pass- Transistors to Bit Lines M1 M3 GND NMOSFETs M5 M6 WL BL BL J.Rabey, Digital Integrated Circuits, Prentice Hall, 1996

13 SEU mapping in an SRAM cell Basic SRAM Test Vehicle (6 transistors) 1193pJ 10 µm 588pJ 891pJ 10pJ Red points 49pJ = Single-Event Upset = flip of the logical state induced by a single laser pulse 30pJ 120pJ 177pJ 305pJ Laser Pulse Energy P. Fouillat, EWRHE 2004 SEU sensitivity map SEU mechanisms Rate prediction Design optimisation

14 SEU Laser cross section in SRAM 177pJ 305pJ 588pJ 891pJ 1193pJ 1E-5 120pJ 49pJ Cross section (cm²) 1E-6 1E-7 1E-8 30pJ 1E-9 10pJ Incident energy (pj) P. Fouillat, EWRHE 2004

15 Testing SRAMs: heavy ions vs. laser HITACHI A 4Mbits 0.5µm versus NEC 1Mbits 0.8µm Laser Tests Heavy ion Tests Laser SEU cross section (cm 2 /device) ,1 0,01 1E-3 1E-4 1E-5 Hitachi HM628512A NEC µpd431000a SEU cross-section (cm 2 /device) ,1 0,01 1E-3 1E-4 1E-5 Hitachi HM628512A NEC µpd431000a Laser energy (pj) LET (MeV.cm 2.mg -1 ) P. Fouillat, EWRHE 2004

16 Increasing SEU resistance of SRAM cells Different technological steps may be realized to improve the SEU Resistance/tolerance of SRAM cells: Enhance storage capacitance (STMicroelectronics) Use 6T cell design with TFT load devices

17 Thin Film Transistor for 6T SRAM cell

18 Increasing SEU resistance of SRAM cells Different technological steps may be realized to improve the SEU Resistance/tolerance of SRAM cells: Enhance storage capacitance (STMicroelectronics) Use 6T cell design with TFT load devices Use retrograde wells, i.e., highly doped implanted layers in order to reduce charge collection at the drain nodes

19 Retrograde well doping profile R.D. Rung et al., IEEE-TED28, 1981

20 Increasing SEU resistance of SRAM cells Different technological steps may be realized to improve the SEU Resistance/tolerance of SRAM cells: Enhance storage capacitance (STMicroelectronics) Use 6T cell design with TFT load devices Use retrograde wells, i.e., highly doped implanted layers in order to reduce charge collection at the drain nodes Eliminate 10 B from the external passivation layers and internal p-doped B rich regions: nuclear reactions from thermal neutrons are suppressed Use plastic packaging instead of ceramic, reducing the amount of radioactive alpha emitters around the Si chip

21 Critical charge in SRAM: status of the art Usually, critical charge: Q crit = V c. C s V c ~ V G [/2] C s ~ W. L. ε ox / t ox Q c ~ L 2 Collected charge: Q coll ~ L However in SRAM: Q crit = V c. C s + I restore. Τ flip Further, parasitic capacitance from Local Interconnections (LIC) may strongly increase C s thus improving SEU immunity (Samsung, IEDM2002)

22 SRAM/Logic Scaling Trends R. Baumann, RADECS Short Course, 2001

23 SRAM SER evolution P. Dodd, et al., IEEE-TNS50, 2003

24 Logic is going to affect SER R. Baumann, IEEE-TDMR, 2005

25 Multiple bit upset A single ion may flip two bits or more inside the same memory word: MBU Identify safe locations for other bit cells Optimize layout aspect ratio and critical node locations Determine minimum spacing of bits in word line D.G. Mavis, EWRHE 2004

26 Changes in technology vs. SRAM SEU Relative Event Rates per Bit or Device Notional graph of RAM SEU Trends *Electronics manufacturers are concerned with soft error rates (SER) on the ground and are beginning to insert means of reducing SER SEFI Single Event Functional Interrupt BER - Bit Error Rate* Speed kills SETs drive increase SEL Single Event Latchup Time Feature size shrinkage

27 Floating Gate memories overview (CG) (FG) Tunnel Oxide Main reliability issues: - Endurance (W/R/E cycles) - Data retention Electrons stored in the FG V TH grows Writing (Flash): Channel Hot Electron tunnelling Erasing (Flash): Fowler- Nordheim tunnelling

28 V TH spatial distribution After 2x10 7 Iodine ions/cm 2 - V TH All cells programmed to 1 Arrows: V TH >2V Multiple Hits on a cell (~1.5% of hit 3 bits with V TH <4V cells) G. Cellere et al., IEEE TNS48, 2001

29 Retention properties of Floating Gate memories FG cells should ensure a data retention time of 10 yrs at room temperature: low leakage from FG Accelerated electrical stresses are customarily performed in order to verify that Write/Erase electrical operations at high fields do not endanger the long time retention properties Appearance of single failing bits is a big concern! Data retention properties of irradiated FG cells: an open question

30 V TH statistical distribution 0.15µm 2 FG devices I ion irradiation A secondary peak appears at ~6V The very low V TH tail is probably due to double hits (1.5% of hit cells at this fluence) Number of cells Fresh After 2x10 7 I ions /cm V TH (V) No known mechanism can explain this large charge loss

31 Data retention in hit FG cells Hit devices only were reprogrammed After only 30min a clear tail appears which increases more and more with time Cumulative probability 99.99% 93.4% 30.7% 4.8% 0.67% 0.09% 0.012% 0.002% 0.04µm 2 (small) devices After 20 days After 30 min V TH (V) After 20 days, V TH ~ 4V After program

32 Model vs. experimental data Experimental data obtained from 0.04µm 2 device irradiated with I previously shown Bars variance (spread) of experimental data Lines calculations IG (A) Experimental Simulated F OX (MV/cm) With 20 defects, good agreement on: Mean value Extreme values (spread)

33 Conclusions Reversed biased junctions of off-state MOSFET drains collect charge produced by a single ionizing particle, possibly leading to SRAM cell bit flip In SRAM SEU cross section saturates at high LET Critical charge for upset decreases with CMOS minimum feature size, but it may be enhanced by parasitic capacitances coming from interconnections SBU s can be compensated by EDAC; MBU s are much less likely but more dangerous SEU rate of SRAM cell array is not increasing with memory generation, but new problems may come from upsets in the circuit external to the memory array and SE Transients Permanent damage may affect RAM and non-volatile memories as well