! Memory. " RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell. " Used in most commercial chips

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1 ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 3, 8 Memory: Core Cells Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery Penn ESE 57 Spring 8 - Khanna Memory Overview Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH L-K Bit Line Storage Cell A K A K+ A L- Row Decoder Word Line Sense Amplifiers / Drivers M. K Amplify swing to rail-to-rail amplitude A A K- Column Decoder Selects appropriate word Input-Output (M bits) Penn ESE 57 Spring 8 - Khanna Read-Write Memories (RAM)! Static (SRAM) " Data stored as long as supply is applied " Large (6 transistors/cell) " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (-3 transistors/cell) " Slower " Single ended 6T SRAM Cell! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge, bit " Raise word! Write: " Drive data onto, " Raise bit_b Penn ESE 57 Spring 8 - Khanna 6

2 6-transistor CMOS SRAM Cell 6-transistor CMOS SRAM Cell Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (stored ) Assume is stored (Q=) Q = Q = M Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (Read) Assume is stored (Q=) Read Operation: - First bitlines get precharged high (Vdd) - Then wordline goes high (Vdd) V Q = M Q = Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna

3 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) Q = Q = Q = Q = V M V M k n, ΔV V Tn Penn ESE 57 Spring 8 - Khanna ( ) = k n,m ( V Tn )ΔV ΔV W k n,m L ( V DD ΔV V Tn ) = = k n,m 5 W (V L DD V Tn )ΔV ΔV Penn ESE 57 Spring 8 - Khanna 5 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) V Q = M Q = Voltage Rise (V) W k n,m L ( V DD ΔV V Tn ) = = k n,m 5 W (V L DD V Tn )ΔV ΔV Penn ESE 57 Spring 8 - Khanna 5 ΔV =V Tn W L ( V DD V Tn ) = W (V DD.5V Tn )V Tn L Cell Ratio (CR).5 3 CMOS SRAM Analysis (Read) 6-transistor CMOS SRAM Cell V Q = M Q = Assume is stored (Q=) Write Operation: - Want to write a - First drive bitlines with input data - Then wordline goes high (Vdd) Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna 3

4 CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) Q = Q = Q = Q = M M = = = = ( ) = k n,m 4 ( V Tp )V Q V Q k n,m 6 V Tn Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) Q = Q = Q = Q = PR = W 4 L 4 W 6 L 6 M M = = = = k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V Q V Q k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V Q V Q V Q =V Tn k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V Tn V Tn Penn ESE 57 Spring 8 - Khanna Penn ESE 57 Spring 8 - Khanna CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) PR = W 4 L 4 W 6 L 6 Q = Q = PR = W 4 L 4 W 6 L 6 M = = Penn ESE 57 Spring 8 - Khanna 4

5 Consider (5T SRAM)! How should we size the devices for read and write without faults? Reminder: Charge Sharing! Initially " V " V! Q A =V*C=C Close switch! Q tot =V final *(C+C)! Charge conservation " Q A =Q tot! C=V final *(C+C) V final = C C+ C Penn ESE 37 Fall 8 - Khanna 5 Penn ESE 37 Fall 8 - Khanna 6 Consider! Read: What happens to voltage at A when turns from #? " Assume W access large " W access >> W pu = " initially " A initially Voltage After enable Word Line! Q =! Q A = (V)(γ(+W access )C )! ff=c >>C A =(γ(+w access )C )! After enable W access (W access large) " Total charge Q +Q A unchanged " Charge conservation " Distributed over larger capacitance~=c " V A =V ~= C A /C C V final = C+ C Penn ESE 37 Fall 8 - Khanna 7 Penn ESE 37 Fall 8 - Khanna 8 Simulation: W access = Larger Resistance?! What happens if W access small? " W access < W pu Penn ESE 37 Fall 8 - Khanna 9 Penn ESE 37 Fall 8 - Khanna 3 5

6 Larger Resistance? Simulation! What happens if W access small? " W access < W pu! Takes time to move charge from A to! Moves more slowly than replenished by W pu Penn ESE 37 Fall 8 - Khanna 3 Penn ESE 37 Fall 8 - Khanna 3 Charge Sharing Consider (5T SRAM)! Conclude: charge sharing can pull down voltage! What happens to voltage at A when reading " I.e when turns from #? " Assume W access large " Bit cell stores a " A initially " precharged to " B initially Penn ESE 37 Fall 8 - Khanna 33 Penn ESE 37 Fall 8 - Khanna 34 Simulation W access = Simulation W access =4 Penn ESE 37 Fall 8 - Khanna 35 Penn ESE 37 Fall 8 - Khanna 36 6

7 Charge Sharing How might we avoid?! Conclude: charge sharing can lead to read upset " Charge redistribution adequate to flip state of bit Penn ESE 37 Fall 8 - Khanna 37 Penn ESE 37 Fall 8 - Khanna 38 Charge to middle Voltage Simulation W access =! Pre-charge bitlines to V dd / before begin read operation! Now charge sharing doesn t swing to opposite side of midpoint Penn ESE 37 Fall 8 - Khanna 39 Penn ESE 37 Fall 8 - Khanna 4 Compare Simulation W access = (precharge Vdd/, reading )! Both W access =; vary precharge voltage Penn ESE 37 Fall 8 - Khanna 4 Penn ESE 37 Fall 8 - Khanna 4 7

8 Simulation W access = (with precharge Vdd/) Pre-Charge V dd / Reference! Use one phase of clock to charge a node to some initial value before operation Penn ESE 37 Fall 8 - Khanna 43 Penn ESE 37 Fall 8 - Khanna 44 Multiple Ports Dual-Ported SRAM! We have considered single-ported SRAM " One read or one write on each cycle! Multiported SRAM are needed for register files! Examples: " Pipelined ALU register file: " add r,r,r3 " R3$R+R " Requires two reads and one write! Simple dual-ported SRAM " Two independent single-ended reads " Or one differential write worda wordb bit bit_b Penn ESE 37 Fall 8 - Khanna 45 Penn ESE 37 Fall 8 - Khanna 46 Dual-Ported SRAM Multi-Ported SRAM! Simple dual-ported SRAM " Two independent single-ended reads " Or one differential write! Adding more access transistors hurts read stability! Multiported SRAM isolates reads from state node! Single-ended bitlines save area worda wordb bit bit_b! Do two reads and one write by time multiplexing " Read during ph, write during ph Penn ESE 37 Fall 8 - Khanna 47 Penn ESE 37 Fall 8 - Khanna 48 8

9 DRAM 3-Transistor DRAM Cell! Smaller than SRAM! Require data refresh to compensate for leakage W W R R M X M3 M X -VT C S -VT ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a = V W-V Tn 49 -Transistor DRAM Cell DRAM Cell Observations C M C S X GND / C ΔV V V ( PRE V BIT V ) S = = PRE C S + C Write "" Read "" V T sensing / Write: CS is charged or discharged by asserting and. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 5 mv.! T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out! DRAM memory cells are single ended in contrast to SRAM cells! The read-out of the T DRAM cell is destructive " Read and refresh operations are necessary for correct operation! Unlike 3T cell, T cell requires presence of an extra capacitance that must be explicitly included in the design! When writing a into a DRAM cell, a threshold voltage is lost " This charge loss can be circumvented by bootstrapping the word lines to a higher value than Memory Periphery Array Architecture! n words of m bits each! Good regularity easy to design! Very high density if good cells are used 54 9

10 Array Architecture Array Architecture! n words of m bits each! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! Good regularity easy to design! Very high density if good cells are used Array Architecture! n words of m bits each! Good regularity easy to design! Very high density if good cells are used Decoders 57 Decoders Large Decoders! n: n decoder consists of n n-input AND gates! For n > 4, NAND gates become slow " One output needed for each row of memory " Break large gates into multiple smaller gates " Build AND from NAND or NOR gates A3 A A A Static CMOS word A A word word word 8 word word3 word A 4 A word word3 word5 59 6

11 Predecoding Row Select: Precharge NAND! Many of these gates are redundant " Factor out common A3 gates into predecoder A " Saves area " Same path effort A A predecoders of 4 hot predecoded lines word word word word3 word5 6 6 Row Select: Precharge NOR Column Circuitry & Bit-line Conditioning 63 Array Architecture Column Circuitry! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! Some circuitry is required for each column " Bitline conditioning " Precharging " Driving input data to bitline " Sense amplifiers " Column multiplexing (AKA Column Decoders) 65 66

12 Bitline Conditioning! Precharge bitlines high before reads Bitline Conditioning! Precharge bitlines high before reads bit φ bit_b bit φ bit_b Bitline Conditioning Bitline Conditioning! Precharge bitlines high before reads! Precharge bitlines high before reads bit φ bit_b bit φ bit_b! What if pre-charged to Vdd/? " Pros: reduces read-upset " Challenge: generate Vdd/ voltage on chip! What if pre-charged to Vdd/? " Pros: reduces read-upset " Challenge: generate Vdd/ voltage on chip 69 7 Voltage Midpoint Reference Generator Sense Amplifiers! The inverter with input and output tied together settles to the midpoint of the transfer curve where the input and output are equal! The second inverter is driven to the same point. It helps isolate the output from the reference. The pass gate allows you to connect or disconnect this reference voltage to a node.! Bitlines have many cells attached " Ex: 3-kbit SRAM has 8 rows x 56 cols " 8 cells on each bitline! t pd (C/I) ΔV " Even with shared diffusion contacts, 64C of diffusion capacitance (big C) " Discharged slowly through small transistors in each memory cell (small I)! Sense amplifiers are triggered on small voltage swing V (ΔV) V() V PRE ΔV V() 7 Sense amp activated Word line activated t 7

13 Differential Pair Amp! Differential pair requires no clock! But always dissipates static power Clocked Sense Amp! Clocked sense amp saves power! Requires sense_clk after enough bitline swing! Isolation transistors cut off large bitline capacitance sense_b bit P N N P sense bit_b sense_clk bit bit_b isolation transistors N3 regenerative feedback sense sense_b SRAM Read Circuit SRAM Read Circuit Differential Sense Amplifier (one per column) Differential Sense Amplifier (one per column) MP MP MA4 MA5 MA4 MA5 V NOT-C V C V NOT-C V C W BW B M Read Select MA φ S MA3 MA Sense Amp Gain: W BW B M Read Select MA φ S MA3 MA Sense Amp Gain: SRAM Write Circuit SRAM Write Circuit WRITE CKT WRITE CKT () () () () () () () () () () W DATA WB WB OPERATION (M3 ON) W DATA WB WB OPERATION (M3 ON)

14 Column Drivers: Memory Bank Array Architecture Details 8 Tristate Buffer Tristate Buffer! Typically used for signal traveling, e.g. bus! Ideally all devices connected to a bus should be disconnected except for active device reading or writing to bus! Use high-impedance state to simulate disconnecting Input En Output Input Vdd En Output Input En Output Input En Ouptut Z Z Input En En Output Active-high buffer CMOS circuit 8 8 Tristate Inverters Ended here En En Input Output Input Output 83 Penn ESE 57 Spring 8 - Khanna 84 4

15 8x4 Memory with column decoder Read/Write Memory A A (A) Column Select -to-4 Decoder Row Decoder 3 8x4 Memory -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit CS -to- Decoder Column Decoder Tristate Buffer (read) D D D D3 A A Rd/Wr (A) Column Select -to-4 Row Decoder 3 CS 8x4 Memory -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -to- Column Decoder D D D D3 A 85 A 86 Read/Write Memory Read/Write Memory 8x4 Memory 8x4 Memory -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit A -to-4 Row Decoder -bit -bit -bit -bit -bit -bit -bit -bit A -to-4 Row Decoder -bit -bit -bit -bit -bit -bit -bit -bit A 3 -bit -bit -bit -bit -bit -bit -bit -bit A 3 -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit -bit Rd/Wr = Rd/Wr = (A) = Column Select CS -to- Column Decoder D D D D3 (A) = Column Select CS -to- Column Decoder D D D D3 A 87 A 88 Idea Admin! Memory for compact state storage! Share circuitry across many bits " Minimize area per bit # maximize density! Aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers to keep area down! Homework 7 due Thursday! Final Project " Design and layout memory " Handout posted before Thursday class " Due 4/4 (last day of class) " Everyone gets an extension until 5/4 " Keep in mind our final exam is on 4/3 " Leave time to study! Penn ESE 57 Spring 8 - Khanna 89 Penn ESE 57 Spring 8 - Khanna 9 5