PassTransistor Logic


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1 all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material Last lecture Decoders Ratioed logic Today s lecture asstransistor logic Dynamic logic Reading (hapter 6) Logic EE4 3 EE4 4 Logic Example: ND Gate puts witch = N transistors No static consumption EE4 5 EE4 6
2 NMOOnly Only Logic NMOonly witch = 2.5V = 2.5 V.5μm/.25μm x.5μm/.25μm.5μm/.25μm Voltage [V] x = 2.5 V = 2.5 V M n M EE Time [ns] 7 EE4 V does not pull up to 2.5V, but 2.5V V TN Threshold voltage loss causes static power consumption NMO has higher threshold than MO (body effect) 8 NMO Only Logic: Level Restoring Transistor Restorer izing Level Restorer M n M r X M Voltage [V] W/L r =.75/.25 W/L r =.5/.25 Upper limit on restorer size asstransistor pulldown can have several transistors in stack W/L r =./.25 W/L r =.25/.25 EE4 dvantage: ull wing Restorer adds capacitance, takes away pull down current at X Ratio problem 9 EE Time [ps] omplementary ass Transistor Logic olution 2: Transmission Gate (a) verse = 2.5 V = = =+ =+ = ΒÝ = ΒÝ (b) = 2.5 V = V EE4 ND/NND OR/NOR EXOR/NEXOR EE4 2 2
3 Resistance of Transmission Gate ased Multiplexer 3 R n 2. 5 V Rn Resistance, ohms 2 R p R n R p 2.5 V V R p V ou t M.. 2. V ou t, V GND 2 EE4 3 EE4 4 Transmission Gate XOR Delay in Transmission Gate s V V i V i V i+ V n V n (a) M2 R eq R V eq R eq R V i V eq Vi+ n V n M M3/M4 m R eq (b) (c) EE4 5 EE4 6 Delay Optimization Transmission Gate ull dder i i um Generation o arry Generation i i etup i imilar delays for sum and carry EE4 7 EE4 8 3
4 Dynamic MO EE4 Dynamic Logic 9 EE4 static circuits at every point in time (except when switching) the output is connected to either GND or via a low resistance path. fanin of n requires 2n (n Ntype + n type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+ Ntype + type) transistors 2 Dynamic Gate Dynamic Gate lk 2 3 lk DN Two phase operation recharge (LK = ) Evaluate (LK = ) lk lk lk 2 3 lk DN Two phase operation recharge (lk = ) Evaluate (lk = ) lk lk off on off on (()+) EE4 2 EE4 22 onditions on put Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. puts to the gate can make at most one transition during evaluation. put can be in the high impedance state during and after evaluation (DN off), state is stored on roperties of Dynamic Gates Logic function is implemented by the DN only number of transistors is N + 2 (versus 2N for static complementary MO) ull swing outputs (V OL = GND and V OH = ) Nonratioed  sizing of the devices does not affect the logic levels aster switching speeds reduced load capacitance due to lower input capacitance ( in ) reduced load capacitance due to smaller output loading (out) no I sc, so all the current provided by DN goes into discharging EE4 23 EE4 24 4
5 roperties of Dynamic Gates Overall power dissipation usually higher than static MO no static current path ever exists between and GND (including sc ) no glitching higher transition probabilities extra load on lk DN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock Next Lecture roperties of dynamic logic Domino logic EE4 25 EE4 26 5
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