VLSI Design I; A. Milenkovic 1

Size: px
Start display at page:

Download "VLSI Design I; A. Milenkovic 1"

Transcription

1 ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( ) Instructor: leksandar Milenkovic E 7-L Mon. 5:3 PM 6:3 PM, Wen. :3 3:3 PM URL: T: Joel Wilder Labs: Lab# posted (due 9/3/5) Text: MO VLI esign, 3 rd ed., Weste, Harris Review: Introduction, esign Metrics, I Fabrication (Read hapter ); I Fabrication (hapter 3) Today: MO Non-ideal IV, MO Inverter (hapter ) 9/4/5 VLI esign I;. Milenkovic MO Inverter VT eta Ratio NMO off PMO res.5 NMO sat PMO res If β p / β n, switching point will move from / alled skewed gate Other gates: collapse into equivalent inverter (V).5 NMO sat PMO sat.5 NMO res PMO sat NMO res PMO off β p. β = n β p β = n.5 (V) 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 4 Noise Margins How much noise can a gate input see before it does not recognize the input? Logic Levels To maximize noise margins, select logic levels at Logical High Output Range Output haracteristics Input haracteristics V OH NM H V IH Indeterminate V Region IL Logical High Input Range β p /β n > Logical Low Output Range V OL NM L Logical Low Input Range 9/4/5 VLI esign I;. Milenkovic 5 9/4/5 VLI esign I;. Milenkovic 6 VLI esign I;. Milenkovic

2 V OL Logic Levels MO Inverter: witch Model of ynamic ehavior To maximize noise margins, select logic levels at unity gain point of transfer characteristic R p Unity Gain Points V OH lope = - L L β p /β n > R n = = V tn V IL V V IH - V tp 9/4/5 VLI esign I;. Milenkovic 7 9/4/5 VLI esign I;. Milenkovic 8 MO Inverter: witch Model of ynamic ehavior Relative Transistor izing R p L R n L When designing static MO circuits, balance the driving strengths of the transistors by making the PMO section wider than the NMO section to maximize the noise margins and obtain symmetrical characteristics = = Gate response time is determined by the time to charge L through R p (discharge L through R n ) 9/4/5 VLI esign I;. Milenkovic 9 9/4/5 VLI esign I;. Milenkovic witching Threshold V M where = (both PMO and NMO in saturation since V = V G ) V M r /( + r) where r = k p V Tp /k n V Tn witching threshold set by the ratio r, which compares the relative driving strengths of the PMO and NMO transistors Want V M = / (to have comparable high and low noise margins), so want r (W/L) p k n V Tn (V M -V Tn -V Tn /) = (W/L) n k p V Tp ( -V M +V Tp +V Tp /) witch Threshold Example In our generic.5 micron MO process, using the process parameters from slide L3.5, a =.5V, and a minimum size NMO device ((W/L) n of.5) NMO PMO (W/L) p (W/L) n = V T (V) γ(v.5 ) V T (V).63 - k (/V ) 5 x -6-3 x -6 λ(v - ) /4/5 VLI esign I;. Milenkovic 9/4/5 VLI esign I;. Milenkovic VLI esign I;. Milenkovic

3 witch Threshold Example imulated Inverter V M In our generic.5 micron MO process, using the process parameters, a =.5V, and a minimum size NMO device ((W/L) n of.5) NMO PMO V T (V) γ(v.5 ) V T (V).63 - k (/V ) 5 x -6-3 x -6 λ(v - ).6 -. (W/L) p 5 x ( /) = x x (W/L) n -3 x -6 = (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5v V M (V) ~3.4 (W/L) p /(W/L) n Note: x-axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3,.5 and gives V M s of.v,.8v, and.3v Increasing the width of the PMO moves V M towards Increasing the width of the NMO moves V M toward 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 4 3 V OH = V OL = Noise Margins etermining V IH and V IL VIL V M piece-wise linear approximation of VT VIH y definition, V IH and V IL are where d /d = - (= gain) NM H = -V IH NM L = V IL - pproximating: V IH = V M -V M /g V IL = V M + ( -V M )/g o high gain in the transition region is very desirable 9/4/5 VLI esign I;. Milenkovic 5 (V) MO Inverter VT from imulation (V).5um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) =.5V V M.5V, g = -7.5 V IL =.V, V IH =.3V NM L = NM H =. (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance low-output =.4kΩ high-output = 3.3kΩ 9/4/5 VLI esign I;. Milenkovic 6 gain Gain eterminates Gain is a strong function of the slopes of the currents in the saturation region, for = V M (+r) g (V M -V Tn -V Tn /)(λ n - λ p ) etermined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing). 9/4/5 VLI esign I;. Milenkovic 7 Impact of Process Variation on VT urve (V) ad PMO Good NMO (V) Good PMO ad NMO Nominal process variations (mostly) cause a shift in the switching threshold 9/4/5 VLI esign I;. Milenkovic 8 VLI esign I;. Milenkovic 3

4 caling the upply Voltage.5..5 (V).5 (V).5 Gain= (V).5.5 (V) evice threshold voltages are evice threshold voltages are kept (virtually) constant kept (virtually) constant 9/4/5 VLI esign I;. Milenkovic 9..5 tatic MO Logic MO ircuit tyles tatic omplementary MO tatic complementary MO - except during switching, output connected to either V or via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at V and, respectively low output impedance, high input impedance no steady state path between V and (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic MO - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise 9/4/5 VLI esign I;. Milenkovic Pull-up network () and pull-down network (PN) In In In N In In In N PN PMO transistors only pull-up: make a connection from to F when F(In,In, In N ) = F(In,In, In N ) pull-down: make a connection from F to when F(In,In, In N ) = NMO transistors only and PN are dual logic networks 9/4/5 VLI esign I;. Milenkovic Threshold rops Threshold rops V G -V Tn L L L L PN L L PN L V G L V Tp 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 4 VLI esign I;. Milenkovic 4

5 onstruction of PN NMO devices in series implement a NN function NMO devices in parallel implement a NOR function + ual and PN and PN are dual networks emorgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the corresponds to a series connection of the PN omplementary gate is naturally inverting (NN, NOR, OI, OI) Number of transistors for an N-input logic gate is N 9/4/5 VLI esign I;. Milenkovic 5 9/4/5 VLI esign I;. Milenkovic 6 MO NN MO NN F NN F = NN(,) F = = F= = = F= = = F= = = F= 9/4/5 VLI esign I;. Milenkovic 7 9/4/5 VLI esign I;. Milenkovic 8 MO NOR MO NOR F NOR F = NOR(,) F + = = = = = F= = F= = F= = F= 9/4/5 VLI esign I;. Milenkovic 9 9/4/5 VLI esign I;. Milenkovic 3 VLI esign I;. Milenkovic 5

6 omplex MO Gate omplex MO Gate OUT =!( + ( + )) OUT =!( + ( + )) 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 3 NOR NOR/OR Implementation 9/4/5 VLI esign I;. Milenkovic 33 How many transistors in each? OR an you create the stick transistor layout for the lower left circuit? ombinational Logic ells MO logic cells N-OR-INVERT (OI) OR-N-INVERT(OI) Example: OI Z = (* + * + E) Z = OI(,,,, E) Exercise: onstruct this logic cell? Example: OI3 Z = [(++)*(+E)*F] Z = OI3(,,,, E, F) Exercise: onstruct this logic cell? OI nd Or Inverter 9/4/5 VLI esign I;. Milenkovic 34 E Z OI tandard ell Layout Methodology Routing channel E signals Z E 9/4/5 VLI esign I;. Milenkovic 35 What logic function is this? 9/4/5 VLI esign I;. Milenkovic 36 VLI esign I;. Milenkovic 6

7 OI Logic Graph Two tick Layouts of!( ( + )) j i =!( ( + )) i j PN uninterrupted diffusion strip 9/4/5 VLI esign I;. Milenkovic 37 9/4/5 VLI esign I;. Milenkovic 38 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i i j j For a single poly strip for every input signal, the Euler paths in the and PN must be consistent (the same) 9/4/5 VLI esign I;. Milenkovic 39 For a single poly strip for every input signal, the Euler paths in the and PN must be consistent (the same) 9/4/5 VLI esign I;. Milenkovic 4 OI Logic Graph OI Layout =!((+) (+)) PN ome functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) 9/4/5 VLI esign I;. Milenkovic 4 9/4/5 VLI esign I;. Milenkovic 4 VLI esign I;. Milenkovic 7

8 ombinational Logic ells (cont d) The OI family of cells with 3 index numbers or less = {OI, OI, O, O}; a,b,c={,3} ell Type a a ab ab abc Total, 3, 3 ells, 33, 3, 3, 33, 333, 33, 3 Number of Unique ells /4/5 VLI esign I;. Milenkovic 43 V G = V V V G = V M 3 M 4 M M VT is ata-ependent F= int 9/4/5 VLI esign I;. Milenkovic 44 3 weaker.5µ/.5µ NMO.75µ /.5µ PMO,: -> =, : -> =, :-> The threshold voltage of M is higher than M due to the body effect (γ) V Tn = V Tn V Tn = V Tn + γ( ( φ F + t ) - φ F ) since V of M is not zero (when V = ) due to the presence of int tatic MO Full dder ircuit! out =! in & (!!) (! &!) tatic MO Full dder ircuit!um = out & (!!! in ) (! &! &! in ) in in in! out!um in in in! out!um in in in in out = in & ( ) ( & ) um =! out & ( in ) ( & & in ) 9/4/5 VLI esign I;. Milenkovic 45 9/4/5 VLI esign I;. Milenkovic 46 VLI esign I;. Milenkovic 8

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe57-3f

More information

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

More information

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties. CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University

More information

CPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles

CPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit

More information

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In

More information

EEE 421 VLSI Circuits

EEE 421 VLSI Circuits EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

More information

Pass-Transistor Logic

Pass-Transistor Logic -all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material

More information

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

B.Supmonchai August 1st, q In-depth discussion of CMOS logic families. q Optimizing gate metrics. q High Performance circuit-design techniques

B.Supmonchai August 1st, q In-depth discussion of CMOS logic families. q Optimizing gate metrics. q High Performance circuit-design techniques ugust st, 4 Goals of This hapter hapter 6 Static MOS ircuits oonchuay Supmonchai Integrated esign pplication Research (IR) Laboratory ugust, 4; Revised - June 8, 5 In-depth discussion of MOS logic families

More information

CMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline

CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-05f

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

Course Administration. CPE/EE 427, CPE 527 VLSI Design I L04: MOS Transistors. Review: CMOS Process at a Glance

Course Administration. CPE/EE 427, CPE 527 VLSI Design I L04: MOS Transistors. Review: CMOS Process at a Glance Course Administration CPE/EE 7, CPE 7 VLI esign I L: MO Transistors epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

More information

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

Lecture 4: DC & Transient Response

Lecture 4: DC & Transient Response Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

5. CMOS Gate Characteristics CS755

5. CMOS Gate Characteristics CS755 5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate. Copy Right by Wentai Liu MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

More information

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 Review: implified CMO Inverter Process CPE/EE 7, CPE 7 VLI esign I L: MO Transistor cut line epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic (

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

COMBINATIONAL LOGIC. Combinational Logic

COMBINATIONAL LOGIC. Combinational Logic COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

More information

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

DC & Transient Responses

DC & Transient Responses ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

Homework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout

Homework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout 0/6/06 Homework # Lecture 8, 9: Sizing and Layout of omplex MOS Gates Reading: hapter 4, sections 4.3-4.5 October 3 & 5, 06 hapter, section.5.5 Prof. R. Iris ahar Weste & Harris vailable on course webpage

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

Static CMOS Circuits

Static CMOS Circuits Static MOS ircuits l onventional (ratio-less) static MOS» overed so far l Ratio-ed logic (depletion load, pseudo nmos) l ass transistor logic ombinational vs. Sequential Logic In Logic ircuit In Logic

More information

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

EECS 141 F01 Lecture 17

EECS 141 F01 Lecture 17 EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND

More information

Digital EE141 Integrated Circuits 2nd Combinational Circuits

Digital EE141 Integrated Circuits 2nd Combinational Circuits Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br

More information

EE141. Administrative Stuff

EE141. Administrative Stuff -Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw

More information

VLSI Circuit Design (EEC0056) Exam

VLSI Circuit Design (EEC0056) Exam Mestrado Integrado em Engenharia Eletrotécnica e de omputadores VLSI ircuit esign (EE0056) Exam 205/6 4 th year, 2 nd sem. uration: 2:30 Open notes Note: The test has 5 questions for 200 points. Show all

More information

COMP 103. Lecture 16. Dynamic Logic

COMP 103. Lecture 16. Dynamic Logic COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic

More information

Motivation for Lecture. For digital design we use CMOS transistors. Gate Source. CMOS symboler. MOS transistor. Depletion. A channel is created

Motivation for Lecture. For digital design we use CMOS transistors. Gate Source. CMOS symboler. MOS transistor. Depletion. A channel is created Motivation for Lecture igital Integrated ircuits iktor Öwall o see how standard gates are implemented with transistors? How does technology affect the performance, e.g. speed and power consumption? What

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 Review Voltage wing of PT Driving an Inverter PE/EE 47, PE 57 VLI Design I L9: MO & Wire apacitances Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic

More information

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

More information

4.10 The CMOS Digital Logic Inverter

4.10 The CMOS Digital Logic Inverter 11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p

More information

Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance

More information

ECE321 Electronics I

ECE321 Electronics I ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS

More information

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 Why Power Matters PE/EE 47, PE 57 VLSI Design I L5: Power and Designing for Low Power Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

More information

EE115C Digital Electronic Circuits Homework #4

EE115C Digital Electronic Circuits Homework #4 EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 ourse dmnstraton PE/EE 47, PE 57 VLI esgn I L8: Pass Transstor Logc epartment of Electrcal and omputer Engneerng Unversty of labama n Huntsvlle leksandar Mlenkovc ( www. ece.uah.edu/~mlenka ) www. ece.uah.edu/~mlenka/cpe57-

More information

Lecture 4: Implementing Logic in CMOS

Lecture 4: Implementing Logic in CMOS Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) ()

More information

Important! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model

Important! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model - Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you

More information

CMOS Technology for Computer Architects

CMOS Technology for Computer Architects CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) 1 2 Recap Threshold Voltage

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare. ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler

More information

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides

More information

Digital Integrated Circuits

Digital Integrated Circuits Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

More information

Topic 4. The CMOS Inverter

Topic 4. The CMOS Inverter Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

More information

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

More information

Chapter # 3: Multi-Level Combinational Logic

Chapter # 3: Multi-Level Combinational Logic hapter # 3: Multi-Level ombinational Logic ontemporary Logic esign Randy H. Katz University of alifornia, erkeley June 993 No. 3- hapter Overview Multi-Level Logic onversion to NN-NN and - Networks emorgan's

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM

More information

EE40 Lec 20. MOS Circuits

EE40 Lec 20. MOS Circuits EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1 Bias circuits OUTLINE Smallsignal

More information

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain rain G Gate

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 The -bit inary dder CPE/EE 427, CPE 527 VLI Design I L2: dder Design Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

Digital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman

Digital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman Digital Microelectronic ircuits (361-1-3021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation. Where Does Power Go in CMOS? Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

More information

ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania, updated 12Feb15

ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania, updated 12Feb15 ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS 1 VDD Vout Vin Ideal VTC Logic 0 = 0 V Logic 1 = VDD 0 2 VOH VDD VOL 0 o.c. Cout For DC steady-state Cout is open circuit. VDD 0 VDD VOL VT0n

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters - III Hello, and welcome to today

More information

Field-Effect (FET) transistors

Field-Effect (FET) transistors Field-Effect (FET) transistors References: Barbow (Chapter 8), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and, therefore, its current-carrying

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

More information