Based on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance


 Lionel Green
 3 years ago
 Views:
Transcription
1 ased on slides/material by Topic 3 J. Rabaey Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris Weste and Harris, MOS VLSI Design: ircuits and Systems Perspective, ddison Wesley Peter Y. K. heung Department of Electrical & Electronic Engineering Imperial ollege London Recommended Reading: J. Rabaey et. al. Digital Integrated ircuits: Design Perspective : hapter 5 (5. 5.3), hapter 6 URL: Weste and Harris, MOS VLSI Design: ircuits and Systems Perspective : hapter (.5), hapter 6 (6., 6.) Topic 3  Topic 3  line The MOS Inverter: irst Glance MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristates and Multipleers Topic 33 Topic 34
2 MOS Inverters Inverter D Response PMOS Polysilicon In. μm =λ Metal D Response: vs. for a gate Inverter When = > = When = > = In between, depends on transistor size and current y KL, must settle such that I dsn = I dsp Transfer function can be found by solving equations, but graphical solution gives more insight urrent depends on region of transistor behavior (cutoff, linear, saturation) NMOS I dsp I dsn Topic 35 Topic 36 nmos Operation pmos Operation utoff Linear Saturated utoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V gsp > V tp V gsp < V tp V gsp < V tp < V tn > V tn > V tn > + V tp < + V tp < + V tp V dsn < V gsn V tn V dsn > V gsn V tn V dsp > V gsp V tp V dsp < V gsp V tp < V tn > V tn > V tp < V tp V gsn = V dsn = I dsp I dsn V gsp =  V tp < V dsp =  I dsp I dsn Topic 37 Topic 38
3 Operating Regions Load Line nalysis urrent vs Vout, Vin or a given : I dsp Vout Region nmos pmos Plot I dsn, I dsp vs. must be where currents are equal in I dsn utoff Linear Saturation Saturation Linear Saturation D E Linear Linear Saturation utoff D E V tn / +V tp Topic 39 Topic 3  D Transfer urve eta Ratio Transcribe points onto vs. plot Eact switching point depends on β p / β n If β p / β n, switching point will move from / Otherwise: D E V tn / +V tp β p. β = n β p β = n.5 Topic 3  Topic 3 
4 Noise Margins Logic Levels How much noise can a gate input see before it does not recognize the input? To maimize noise margins, select logic levels at unity gain point of D transfer characteristic Logical High put Range put haracteristics V OH NM H V IH V IL Input haracteristics Indeterminate Region Logical High Input Range V OH Unity Gain Points Slope =  β p /β n > Logical Low put Range V OL NM L Logical Low Input Range V OL V tn V IL V IH  V tp Topic 33 Topic 34 Transient Response Inverter Step Response D analysis tells us if is constant Transient analysis tells us (t) if (t) changes Requires solving differential equations Input is usually considered to be a step or ramp rom to or vice versa I V V E: find step response of inverter driving load cap in out () t = ut ( t) V ( t < t ) = V DD dvo ut ( t) Id = dt sn DD () t load ( ) t t β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () out t Vout < VDD Vt (t) t I dsn (t) (t) (t) load (t) t Topic 35 Topic 36
5 Ideal Inverter Voltage Transfer haracteristic of Real Inverter NM L g= R i = R o = (V) 3.. V M. NM H (V) Topic 37 Topic 38 line Delay Definitions MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos 5% t phl t plh t 9% 5% Tristates and Multipleers t f % t r t Topic 39 Topic 3 
6 Impact of Rise Time on Delay Simulated Inverter Delay.35.3 Solving differential equations by hand is too hard SPIE simulator solves the equations numerically Uses more accurate IV models too! ut simulations take time to write t phl (nsec) t rise (nsec).8. (V).5 t pdf = 66ps t pdr = 83ps.. p 4p 6p 8p n t(s) Topic 3  Topic 3  Delay Estimation R Delay Models Need to easily estimate delay Not as accurate as simulation ut easier to ask What if? The step response usually looks like a st order R response with a decaying eponential. Use R delay models to estimate delay = total capacitance on output node Use effective resistance R So that t pd = R haracterize transistors by finding their effective R Depends on average current as gate switches Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance Unit pmos has resistance R, capacitance apacitance proportional to width Resistance inversely proportional to width g d k s g R/k k d s k k g d k s g s k R/k k k d Topic 33 Topic 34
7 omputing the apacitances omputing the apacitances M db g4 M4 gd M db w Interconnect g3 M3 anout Simplified Model Topic 35 Topic 36 Delay as a function of line 8 MOS Inverter response delays Normalized Delay (V) Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristates and Multipleers Topic 37 Topic 38
8 Digital Gates undamental Parameters anin and anout unctionality Reliability, Robustness rea Performance Speed (delay) Power onsumption Energy (a) anout N N M (b) anin M Topic 39 Topic 33 ombinational vs. Sequential Logic line In Logic ircuit In Logic ircuit MOS Inverter response delays (a) ombinational State (b) Sequential Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos put = f(in) put = f(in, Previous In) Tristates and Multipleers Topic 33 Topic 33
9 Static MOS ircuit Static MOS t every point in time (ecept during the switching transients) each gate output is connected to either V dd or V ss via a lowresistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. In In In3 PUN PDN PMOS Only = G NMOS Only V SS PUN and PDN are Dual Networks Topic 333 Topic 334 NMOS Transistors in Series/Parallel onnection PMOS Transistors in Series/Parallel onnection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high PMOS switch closes when switch control input is low X Y Y = X if and X Y Y = X if ND = + X Y Y = X if OR X Y Y = X if OR = NMOS Transistors pass a strong but a weak PMOS Transistors pass a strong but a weak Topic 335 Topic 336
10 omplementary MOS Logic Style onstruction NND Gate Topic 337 Topic 338 NOR Gate omple Gates D D OUT = D + (+) Topic 339 Topic 34
11 4input NND Gate Standard ell Layout Methodology Vdd In 4 metal Well In 4 signals V SS Routing hannel polysilicon In In In3 In4 Topic 34 Topic 34 Two Versions of (a+b).c Logic Graph b a j c c i PUN a c b a b c (a) Input order {a c b} (b) Input order {a b c} a c i b b j a PDN Topic 343 Topic 344
12 onsistent Euler Path Eample: = ab+cd b c b c c i a d a d b j a (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} { a b c} a b c d (c) stick diagram for ordering {a b c d} Topic 345 Topic 346 Properties of omplementary MOS Gates Transistor Sizing High noise margins: V OH and V OL are at and, respectively. for symmetrical response (dc, ac) for performance No static power consumption: There never eists a direct path between and V SS () in steadystate mode. omparable rise and fall times: (under the appropriate scaling conditions) D 6 D 6 Input Dependent ocus on worstcase Topic 347 Topic 348
13 Propagation Delay nalysis  The Switch Model What is the Value of R on? = R ON V DD R R p R p R p p R R p n R n R n R n R n (a) Inverter (b) input NND (c) input NOR t p =.69 R on (assuming that dominates!) Topic 349 Topic 35 nalysis of Propagation Delay Design for Worst ase R n R n R p R p. ssume R n =R p = resistance of minimum sized NMOS inverter. Determine Worst ase Input transition (Delay depends on input values) 3. Eample: t plh for input NND  Worst case when only ONE PMOS Pulls up the output node  or PMOS devices in parallel, the resistance is lower t plh =.69R p D 4 4 D input NND 4. Eample: t phl for input NND  Worst case : TWO NMOS in series Here it is assumed that R p = R n Topic 35 t phl =.69(R n ) Topic 35
14 Influence of anin and an on Delay t p as a function of anin 4. D an: Number of Gates onnected Gate apacitances per an 3. t phl D anin: Quadratic Term due to:. Resistance Increasing. apacitance Increasing (t phl ) t p (nsec).. quadratic linear fanin t p t plh t p = a I + a I + a 3 O VOID LRGE NIN GTES! (Typically not more than I < 4) Topic 353 Topic 354 ast omple Gate  Design Techniques ast omple Gate  Design Techniques () Transistor Sizing: s long as anout apacitance dominates Progressive Sizing: Transistor Ordering critical path critical path In N MN M3 M M3 3 M > M > M3 > MN Distributed Rline M M M M M3 3 M an Reduce Delay with more than 3%! (a) (b) Topic 355 Topic 356
15 ast omple Gate  Design Techniques (3) Improved Logic Design ast omple Gate  Design Techniques (4) uffering: Isolate anin from anout Topic 357 Topic 358 Ratioed Logic PseudoNMOS Resistive Load R L Depletion Load V T < PMOS Load V SS PDN PDN PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudonmos The pullup pchannel transistor is always conducting. Disadvantages: high d.c. dissipation & slow rise time. Goal: to reduce the number of devices over complementary MOS Topic 359 Topic 36
16 PseudoNMOS NND Gate Improved Loads M M PDN PDN V SS V SS Dual ascode Voltage Switch Logic (DVSL) Topic 36 Topic 36 PassTransistor Logic NMOSonly switch = 5 V = 5 V Inputs Switch Network = 5 V = 5 V M n M M N transistors V does not pull up to 5V, but 5V  V TN No static consumption Threshold voltage loss causes static power consumption Topic 363 Topic 364
17 Pass Transistor Logic with feedback omplementary Pass Transistor Logic PassTransistor Network (a) Inverse PassTransistor Network = =+ = ΒÝ (b) = =+ = ΒÝ ND/NND OR/NOR EXOR/NEXOR Topic 365 Topic Input NND in PL Transmission Gate = 5 V = 5 V = V Topic 367 Topic 368
18 Pass Transistor XOR gate line MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristates and Multipleers Topic 369 Topic 37 Dynamic Logic Eample M p PDN M e n network M e PUN M p p network M p N + Transistors Ratioless No Static Power onsumption Noise Margins small (NM L ) Requires lock phase operation: Precharge Evaluation M e Topic 37 Topic 37
19 Dynamic 4 Input NND Gate ascading Dynamic Gates V In M p M p In V Tn M e M e ΔV t In 4 (a) Only Transitions allowed at inputs! (b) Topic 373 Topic 374 Domino Logic Domino Logic  haracteristics Only noninverting logic M p M p M r Very fast  Only > transitions at input of inverter move V M upwards by increasing PMOS PDN In 4 PDN Static Inverter with Level Restorer dding level restorer reduces leakage and charge redistribution problems M e M e Optimize inverter for fanout Topic 375 Topic 376
20 npmos MOS ircuit Styles  Summary M p M e PDN In 4 PUN M e M p Only transitions allowed at inputs of PUN Topic 377 Topic 378 line Tristates MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristate buffer produces Z when not enabled EN Y Z Z EN EN Y Y Tristates and Multipleers EN Topic 379 Topic 38
21 Multipleers Gate Level Mu Design : multipleer chooses between two inputs Y = SD + SD (too many transistors) How many transistors are needed? S D X X D X X Y D D S Y D S D D S D 4 4 Y 4 Y Topic 38 Topic 38 Transmission Gate Mu Summary Mu uses two transmission gates Only 4 transistors D D S S S Y Inverter response and delays Three main operating regions (cutoff, linear, saturation) Noise margins t phl, t plh, t f, t r Logic design styles Static (ignores transient effects during switching) onventional static MOS (PUP, PDN networks) Ratioed logic (resistive load on top of PDN network) Pass transistors/transmission gates (one transistor per input/good and values) Dynamic (temporary stores signal values on capacitances of circuit nodes) Domino (cascaded dynamic gates connected through inverters) npmos (cascaded dynamic gates with alternating networks) Topic 383 Topic 384
COMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationStatic CMOS Circuits
Static MOS ircuits l onventional (ratioless) static MOS» overed so far l Ratioed logic (depletion load, pseudo nmos) l ass transistor logic ombinational vs. Sequential Logic In Logic ircuit In Logic
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationDigital EE141 Integrated Circuits 2nd Combinational Circuits
Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationEE141. Administrative Stuff
Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw
More informationCPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationVLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationCPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationPassTransistor Logic
all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Views / bstractions / Hierarchies ehavioral Structural
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratioless) static CMOS Covered so far Ratioed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More informationVLSI Design I; A. Milenkovic 1
PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe573f
More informationB.Supmonchai August 1st, q Indepth discussion of CMOS logic families. q Optimizing gate metrics. q High Performance circuitdesign techniques
ugust st, 4 Goals of This hapter hapter 6 Static MOS ircuits oonchuay Supmonchai Integrated esign pplication Research (IR) Laboratory ugust, 4; Revised  June 8, 5 Indepth discussion of MOS logic families
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
More informationEECS 141 F01 Lecture 17
EECS 4 F0 Lecture 7 With major inputs/improvements From MaryJane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND
More informationVLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )
More informationDigital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman
Digital Microelectronic ircuits (36113021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe5705f
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationDelay and Power Estimation
EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationLecture 81. Low Power Design
Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas Email: k.masselos@ic.ac.uk Lecture 81 Based on slides/material
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationCombinational Logic Design
PEN 35  igital System esign ombinational Logic esign hapter 3 Logic and omputer esign Fundamentals, 4 rd Ed., Mano 2008 Pearson Prentice Hall esign oncepts and utomation topdown design proceeds from
More informationDynamic Combinational Circuits. Dynamic Logic
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic npcmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q PseudonMOS Logic q Dynamic Logic q
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationEE 330 Lecture 39. Digital Circuits. Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates)
EE 330 Lecture 39 Digital ircuits Propagation Delay basic characterization Device Sizing (Inverter and multipleinput gates) Review from last lecture Other MOS Logic Families Enhancement Load NMOS Enhancement
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationChapter 37. An Exercise. Problem 1. Digital ICDesign. Problem. Problem. 1, draw the static transistor schematic for the function Q = (A+BC)D
igital Iesign Problem Parameters rom a.35 um process hapter 37 n Exercise, draw the static transistor schematic or the unction (+), ind the corresponding domino gate using a PN net 3, ind the Euler path
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationCMOS Logic Gates. University of Connecticut 172
CMOS Logic Gates University of Connecticut 172 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More information