Based on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance


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1 ased on slides/material by Topic 3 J. Rabaey Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris Weste and Harris, MOS VLSI Design: ircuits and Systems Perspective, ddison Wesley Peter Y. K. heung Department of Electrical & Electronic Engineering Imperial ollege London Recommended Reading: J. Rabaey et. al. Digital Integrated ircuits: Design Perspective : hapter 5 (5. 5.3), hapter 6 URL: Weste and Harris, MOS VLSI Design: ircuits and Systems Perspective : hapter (.5), hapter 6 (6., 6.) Topic 3  Topic 3  line The MOS Inverter: irst Glance MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristates and Multipleers Topic 33 Topic 34
2 MOS Inverters Inverter D Response PMOS Polysilicon In. μm =λ Metal D Response: vs. for a gate Inverter When = > = When = > = In between, depends on transistor size and current y KL, must settle such that I dsn = I dsp Transfer function can be found by solving equations, but graphical solution gives more insight urrent depends on region of transistor behavior (cutoff, linear, saturation) NMOS I dsp I dsn Topic 35 Topic 36 nmos Operation pmos Operation utoff Linear Saturated utoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V gsp > V tp V gsp < V tp V gsp < V tp < V tn > V tn > V tn > + V tp < + V tp < + V tp V dsn < V gsn V tn V dsn > V gsn V tn V dsp > V gsp V tp V dsp < V gsp V tp < V tn > V tn > V tp < V tp V gsn = V dsn = I dsp I dsn V gsp =  V tp < V dsp =  I dsp I dsn Topic 37 Topic 38
3 Operating Regions Load Line nalysis urrent vs Vout, Vin or a given : I dsp Vout Region nmos pmos Plot I dsn, I dsp vs. must be where currents are equal in I dsn utoff Linear Saturation Saturation Linear Saturation D E Linear Linear Saturation utoff D E V tn / +V tp Topic 39 Topic 3  D Transfer urve eta Ratio Transcribe points onto vs. plot Eact switching point depends on β p / β n If β p / β n, switching point will move from / Otherwise: D E V tn / +V tp β p. β = n β p β = n.5 Topic 3  Topic 3 
4 Noise Margins Logic Levels How much noise can a gate input see before it does not recognize the input? To maimize noise margins, select logic levels at unity gain point of D transfer characteristic Logical High put Range put haracteristics V OH NM H V IH V IL Input haracteristics Indeterminate Region Logical High Input Range V OH Unity Gain Points Slope =  β p /β n > Logical Low put Range V OL NM L Logical Low Input Range V OL V tn V IL V IH  V tp Topic 33 Topic 34 Transient Response Inverter Step Response D analysis tells us if is constant Transient analysis tells us (t) if (t) changes Requires solving differential equations Input is usually considered to be a step or ramp rom to or vice versa I V V E: find step response of inverter driving load cap in out () t = ut ( t) V ( t < t ) = V DD dvo ut ( t) Id = dt sn DD () t load ( ) t t β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () out t Vout < VDD Vt (t) t I dsn (t) (t) (t) load (t) t Topic 35 Topic 36
5 Ideal Inverter Voltage Transfer haracteristic of Real Inverter NM L g= R i = R o = (V) 3.. V M. NM H (V) Topic 37 Topic 38 line Delay Definitions MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos 5% t phl t plh t 9% 5% Tristates and Multipleers t f % t r t Topic 39 Topic 3 
6 Impact of Rise Time on Delay Simulated Inverter Delay.35.3 Solving differential equations by hand is too hard SPIE simulator solves the equations numerically Uses more accurate IV models too! ut simulations take time to write t phl (nsec) t rise (nsec).8. (V).5 t pdf = 66ps t pdr = 83ps.. p 4p 6p 8p n t(s) Topic 3  Topic 3  Delay Estimation R Delay Models Need to easily estimate delay Not as accurate as simulation ut easier to ask What if? The step response usually looks like a st order R response with a decaying eponential. Use R delay models to estimate delay = total capacitance on output node Use effective resistance R So that t pd = R haracterize transistors by finding their effective R Depends on average current as gate switches Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance Unit pmos has resistance R, capacitance apacitance proportional to width Resistance inversely proportional to width g d k s g R/k k d s k k g d k s g s k R/k k k d Topic 33 Topic 34
7 omputing the apacitances omputing the apacitances M db g4 M4 gd M db w Interconnect g3 M3 anout Simplified Model Topic 35 Topic 36 Delay as a function of line 8 MOS Inverter response delays Normalized Delay (V) Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristates and Multipleers Topic 37 Topic 38
8 Digital Gates undamental Parameters anin and anout unctionality Reliability, Robustness rea Performance Speed (delay) Power onsumption Energy (a) anout N N M (b) anin M Topic 39 Topic 33 ombinational vs. Sequential Logic line In Logic ircuit In Logic ircuit MOS Inverter response delays (a) ombinational State (b) Sequential Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos put = f(in) put = f(in, Previous In) Tristates and Multipleers Topic 33 Topic 33
9 Static MOS ircuit Static MOS t every point in time (ecept during the switching transients) each gate output is connected to either V dd or V ss via a lowresistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. In In In3 PUN PDN PMOS Only = G NMOS Only V SS PUN and PDN are Dual Networks Topic 333 Topic 334 NMOS Transistors in Series/Parallel onnection PMOS Transistors in Series/Parallel onnection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high PMOS switch closes when switch control input is low X Y Y = X if and X Y Y = X if ND = + X Y Y = X if OR X Y Y = X if OR = NMOS Transistors pass a strong but a weak PMOS Transistors pass a strong but a weak Topic 335 Topic 336
10 omplementary MOS Logic Style onstruction NND Gate Topic 337 Topic 338 NOR Gate omple Gates D D OUT = D + (+) Topic 339 Topic 34
11 4input NND Gate Standard ell Layout Methodology Vdd In 4 metal Well In 4 signals V SS Routing hannel polysilicon In In In3 In4 Topic 34 Topic 34 Two Versions of (a+b).c Logic Graph b a j c c i PUN a c b a b c (a) Input order {a c b} (b) Input order {a b c} a c i b b j a PDN Topic 343 Topic 344
12 onsistent Euler Path Eample: = ab+cd b c b c c i a d a d b j a (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} { a b c} a b c d (c) stick diagram for ordering {a b c d} Topic 345 Topic 346 Properties of omplementary MOS Gates Transistor Sizing High noise margins: V OH and V OL are at and, respectively. for symmetrical response (dc, ac) for performance No static power consumption: There never eists a direct path between and V SS () in steadystate mode. omparable rise and fall times: (under the appropriate scaling conditions) D 6 D 6 Input Dependent ocus on worstcase Topic 347 Topic 348
13 Propagation Delay nalysis  The Switch Model What is the Value of R on? = R ON V DD R R p R p R p p R R p n R n R n R n R n (a) Inverter (b) input NND (c) input NOR t p =.69 R on (assuming that dominates!) Topic 349 Topic 35 nalysis of Propagation Delay Design for Worst ase R n R n R p R p. ssume R n =R p = resistance of minimum sized NMOS inverter. Determine Worst ase Input transition (Delay depends on input values) 3. Eample: t plh for input NND  Worst case when only ONE PMOS Pulls up the output node  or PMOS devices in parallel, the resistance is lower t plh =.69R p D 4 4 D input NND 4. Eample: t phl for input NND  Worst case : TWO NMOS in series Here it is assumed that R p = R n Topic 35 t phl =.69(R n ) Topic 35
14 Influence of anin and an on Delay t p as a function of anin 4. D an: Number of Gates onnected Gate apacitances per an 3. t phl D anin: Quadratic Term due to:. Resistance Increasing. apacitance Increasing (t phl ) t p (nsec).. quadratic linear fanin t p t plh t p = a I + a I + a 3 O VOID LRGE NIN GTES! (Typically not more than I < 4) Topic 353 Topic 354 ast omple Gate  Design Techniques ast omple Gate  Design Techniques () Transistor Sizing: s long as anout apacitance dominates Progressive Sizing: Transistor Ordering critical path critical path In N MN M3 M M3 3 M > M > M3 > MN Distributed Rline M M M M M3 3 M an Reduce Delay with more than 3%! (a) (b) Topic 355 Topic 356
15 ast omple Gate  Design Techniques (3) Improved Logic Design ast omple Gate  Design Techniques (4) uffering: Isolate anin from anout Topic 357 Topic 358 Ratioed Logic PseudoNMOS Resistive Load R L Depletion Load V T < PMOS Load V SS PDN PDN PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudonmos The pullup pchannel transistor is always conducting. Disadvantages: high d.c. dissipation & slow rise time. Goal: to reduce the number of devices over complementary MOS Topic 359 Topic 36
16 PseudoNMOS NND Gate Improved Loads M M PDN PDN V SS V SS Dual ascode Voltage Switch Logic (DVSL) Topic 36 Topic 36 PassTransistor Logic NMOSonly switch = 5 V = 5 V Inputs Switch Network = 5 V = 5 V M n M M N transistors V does not pull up to 5V, but 5V  V TN No static consumption Threshold voltage loss causes static power consumption Topic 363 Topic 364
17 Pass Transistor Logic with feedback omplementary Pass Transistor Logic PassTransistor Network (a) Inverse PassTransistor Network = =+ = ΒÝ (b) = =+ = ΒÝ ND/NND OR/NOR EXOR/NEXOR Topic 365 Topic Input NND in PL Transmission Gate = 5 V = 5 V = V Topic 367 Topic 368
18 Pass Transistor XOR gate line MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristates and Multipleers Topic 369 Topic 37 Dynamic Logic Eample M p PDN M e n network M e PUN M p p network M p N + Transistors Ratioless No Static Power onsumption Noise Margins small (NM L ) Requires lock phase operation: Precharge Evaluation M e Topic 37 Topic 37
19 Dynamic 4 Input NND Gate ascading Dynamic Gates V In M p M p In V Tn M e M e ΔV t In 4 (a) Only Transitions allowed at inputs! (b) Topic 373 Topic 374 Domino Logic Domino Logic  haracteristics Only noninverting logic M p M p M r Very fast  Only > transitions at input of inverter move V M upwards by increasing PMOS PDN In 4 PDN Static Inverter with Level Restorer dding level restorer reduces leakage and charge redistribution problems M e M e Optimize inverter for fanout Topic 375 Topic 376
20 npmos MOS ircuit Styles  Summary M p M e PDN In 4 PUN M e M p Only transitions allowed at inputs of PUN Topic 377 Topic 378 line Tristates MOS Inverter response delays Logic gates Static MOS onventional Static MOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic MOS Domino npmos Tristate buffer produces Z when not enabled EN Y Z Z EN EN Y Y Tristates and Multipleers EN Topic 379 Topic 38
21 Multipleers Gate Level Mu Design : multipleer chooses between two inputs Y = SD + SD (too many transistors) How many transistors are needed? S D X X D X X Y D D S Y D S D D S D 4 4 Y 4 Y Topic 38 Topic 38 Transmission Gate Mu Summary Mu uses two transmission gates Only 4 transistors D D S S S Y Inverter response and delays Three main operating regions (cutoff, linear, saturation) Noise margins t phl, t plh, t f, t r Logic design styles Static (ignores transient effects during switching) onventional static MOS (PUP, PDN networks) Ratioed logic (resistive load on top of PDN network) Pass transistors/transmission gates (one transistor per input/good and values) Dynamic (temporary stores signal values on capacitances of circuit nodes) Domino (cascaded dynamic gates connected through inverters) npmos (cascaded dynamic gates with alternating networks) Topic 383 Topic 384
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