Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today

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1 EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS

2 Frequency [GHz] Performance Histogram EECS Frequency [GHz] Performance - pruned Power [W] 3.5E E E E E E E E E E E E+09 Frequency [Hz] EECS

3 Max: 98 Avg: 78.9 StDev: Median: EECS141 5 Design implementation of 256-bit code Create floorplan to estimate wirelength Optimize circuit such that energy is minimized for max delay of 10 nsec Determine also Tdmin and Emin for that design Present results in poster Energy (T d,min, E max ) (T d, E) (T d,max, E min ) Delay EECS

4 Template: Group A: Group B: Same but period is 4 Group C: Same but period is 8 Group D: Same but period is 16 EECS141 7! EECS

5 ! EECS141 9 Energy? Joule 10ns Optimization target Delay The extremes EECS

6 Last lecture Multipliers Today s lecture Memory cells Reading (Ch 12) EECS EECS

7 Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM EECS STATIC (SRAM) Data stored as long as supply is applied Larger (6 transistors/cell) Fast Differential (usually) DYNAMIC (DRAM) Periodic refresh required Smaller (1-3 transistors/cell) Slower Single Ended EECS

8 Conceptual: linear array Each box holds some data But this does not lead to a nice layout shape Too long and skinny Create a 2-D array Decode Row and Column address to get data EECS M bits M bits N words S 0 S 1 S 2 S N-2 S N -1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage cell A 0 A 1 A K-1 K = log 2 N D e c o d e r S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage cell Input-Output ( M bits) Input-Output ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Decoder reduces the number of select signals K = log N 2 EECS

9 EECS If D is high, D_b will be driven low Which makes D stay high Positive feedback EECS

10 EECS Access transistor must be able to overpower the feedback EECS

11 EECS Complementary data values are written (read) from two sides EECS

12 WL M 2 M 4 M 5 Q Q M 6 M 1 M 3 BL BL EECS Read 1 0 Q_b will get pulled up when WL first goes high Reading the cell should not destroy the stored value EECS

13 WL BL M 5 Q = 0 Q = 1 M 4 M 6 BL M 1 C bit C bit EECS Voltage Rise (V) Cell Ratio (CR) EECS

14 WL M 4 M 5 Q = 0 Q = 1 M 6 M 1 BL = 1 BL = 0 EECS EECS

15 Obtained by breaking the feedback between the inverters SNM EECS BL BLB Compact cell Bitlines: M2 Wordline: bootstrapped in M3 GND WL EECS

16 ST/Philips/Motorola Access Transistor Pull down Pull up EECS EECS

17 EECS WL R L R L M 3 Q Q M 4 BL M 1 M 2 BL Static power dissipation -- Want R L large Bit lines precharged to to address t p problem EECS

18 BL 1 BL 2 WWL RWL WWL M 3 RWL M 1 X M 2 X - V T C S BL 1 BL 2 - V T D V No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn EECS BL 1 BL 2 BL2 BL1 GND WWL RWL RWL M3 M 3 M2 M 1 X M 2 C S WWL M1 EECS

19 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Δ V BL V PRE V BIT V C S = V = PRE C S + C BL Voltage swing is small; typically around 250 mv. EECS Capacitor Metal word line n + Poly Poly n + Inversion layer induced by plate bias Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Polysilicon plate M 1 word line Uses Polysilicon-Diffusion Capacitance Expensive in Area EECS

20 EECS Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Trench Cell EECS141 Stacked-capacitor Cell 40 20

21 BL BL BL 1 WL WL WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2 EECS Pull-up devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] EECS

22 Cell (9.5λ x 7λ) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion EECS Cell (11λ x 7λ) Programmming using the Contact Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion 44 EECS

23 Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row EECS Cell (8λ x 7λ) Programmming using the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion EECS

24 Cell (5λ x 6λ) Programmming using Implants Only Polysilicon Threshold-altering implant Metal1 on Diffusion 47 EECS Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol EECS

25 20 V 0 V 5 V 10 V 5 V 20 V - 5 V 0 V V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T. EECS Floating gate Gate I Source Drain nm -10 V V GD 10 V n 1 n Substrate 1 p 10 nm FLOTOX transistor Fowler-Nordheim I-V characteristic EECS

26 BL WL Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell EECS Flash Courtesy Intel EPROM EECS

27 Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry EECS Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder EECS

28 Look at decoder for 256x256 memory block (8KBytes) EECS Goal: Build fastest possible decoder with static CMOS logic What we know Basically need 256 AND gates, each one of them drives one word line N=8 EECS

29 Each word line has 256 cells connected to it Total output load is 256*C cell + C wire Assume that decoder input capacitance is C address =4*C cell Each address drives 2 8 /2 AND gates A0 drives ½ of the gates, A0_b the other ½ of the gates Neglecting C wire, the fan-out on each one of the 16 address wires is: B EECS FB of at least 2 13 means that we will want to use more than log 4 (2 13 ) = 6.5 stages to implement the AND8 Need many stages anyways So what is the best way to implement the AND gate? Will see next that it s the one with the most stages and least complicated gates EECS

30 LE=10/3 1 ΠLE = 10/3 P = LE=2 5/3 ΠLE = 10/3 P = LE=4/3 5/3 4/3 1 ΠLE = 80/27 P = EECS Using 2-input NAND gates 8-input gate takes 6 stages Total LE is (4/3) So PE is 2.4*2 13 optimal N of ~7.1 EECS

31 256 8-input AND gates Each built out of tree of NAND gates and inverters Issue: Every address line has to drive 128 gates (and wire) right away Can t build gates small enough - Forces us to add buffers just to drive address inputs EECS EECS

32 Use a single gate for each of the shared terms E.g., from A 0, A 0, A 1, and A 1, generate four signals: A 0 A 1, A 0 A 1, A 0 A 1, A 0 A 1 In other words, we are decoding smaller groups of address bits first And using the predecoded outputs to do the rest of the decoding EECS EECS

33 Multi-stage implementation improves performance WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 EECS Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 0 WL 1 WL 0 φ A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 φ 2-input NOR decoder 2-input NAND decoder EECS

34 BL 0 BL 1 BL 2 BL 3 A 0 S 0 S 1 S 2 A 1 S 3 2-input NOR decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count D EECS BL 0 BL 1 BL 2 BL 3 A 0 A 0 A 1 A 1 Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches EECS D 34

35 t p = C Δ V I av make Δ V as small as possible large Idea: Use Sense Amplifer small EECS M 3 M 4 y Out bit M 1 M 2 bit SE M 5 Directly applicable to SRAMs EECS

36 EECS EQ BL BL SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. EECS