EE141- Spring 2004 Digital Integrated Circuits

Transcription

1 EE141- pring 2004 Digital Integrated ircuits Lecture 19 Dynamic Logic - Adders (that is wrap-up) 1 Administrative tuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week

2 lass Material Last lecture Adders Today s lecture Wrapping up dynamic logic and adders Intro into multipliers 3 Dynamic Logic 4 2

3 Dynamic Gate Out Out In 1 In 2 In 3 PDN L A B Two phase operation Precharge (LK = 0) Evaluate (LK = 1) 5 ome undesirable effects Leakage harge haring lock Feedthrough Backgate oupling 6 3

4 ascading Dynamic Gates V In Out1 Out2 In Out1 V Tn Out2 V t Only 0 1 transitions allowed at inputs! 7 Domino Logic In 1 In PDN Out In 4 M kp PDN Out2 In 3 In 5 8 4

5 Why Domino? In i In j PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! 9 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced smaller logical effort 10 5

6 Designing with Domino Logic V DD V DD V DD Out1 M r Out2 In 1 In 2 PDN In 4 PDN In 3 an be eliminated! Inputs = 0 during precharge 11 Footless Domino The first gate in the chain needs a foot switch Precharge is rippling short-circuit current A solution is to delay the clock for each stage 12 6

7 Differential (Dual Rail) Domino Out = AB off on M kp M kp A B!A!B Out = AB olves the problem of non-inverting logic 13 np-mo In 1 In 2 In 3 PDN Out1 In 4 In 5 PUN Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN 14 7

8 NORA Logic In 1 In 2 In 3 PDN Out1 In 4 In 5 PUN Out2 (to PDN) to other PDN s to other PUN s WARNING: Very sensitive to noise! 15 Adders 16 8

9 Adder Delays - omparison 17 LookAhead - Basic Idea ok, = fa ( k, B k, ok ) = G k + P k ok 1, 1, 18 9

10 Look-Ahead: Topology Expanding Lookahead equations: ok, = G k + P k ( G k 1 + P k 1 ok, 2 ) All the way: o k, = G k + P k ( G k 1 + P k 1 ( + P 1 ( G 0 + P 0 i0, ))) 19 Logarithmic Look-Ahead Adder A 0 F A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 0 A 1 t p N A 2 A 3 A 4 A 5 A 6 A 7 F t p log 2 (N) 20 10

11 arry Lookahead Trees o0, = G 0 + P 0 i0, o, 1 = G 1 + P 1 G 0 + P 1 P 0 i, 0 o, 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 i, 0 = ( G 2 + P 2 G 1 ) + ( P 2 P 1 )( G 0 + P 0 i 0 ) = G 2:1 + P 2:1 o 0 an continue building the tree hierarchically.,, 21 Tree Adders (A 0, B 0 ) (A 1, B 1 ) (A 2, B 2 ) (A 3, B 3 ) (A 4, B 4 ) (A 5, B 5 ) (A 6, B 6 ) (A 7, B 7 ) (A 8, B 8 ) (A 9, B 9 ) (A 10, B 10 ) (A 11, B 11 ) (A 12, B 12 ) (A 13, B 13 ) (A 14, B 14 ) (A 15, B 15 ) bit radix-2 Kogge-tone tree 22 11

12 Tree Adders (a 0, b 0 ) (a 1, b 1 ) (a 2, b 2 ) (a 3, b 3 ) (a 4, b 4 ) (a 5, b 5 ) (a 6, b 6 ) (a 7, b 7 ) (a 8, b 8 ) (a 9, b 9 ) (a 10, b 10 ) (a 11, b 11 ) (a 12, b 12 ) (a 13, b 13 ) (a 14, b 14 ) (a 15, b 15 ) bit radix-4 Kogge-tone Tree 23 parse Trees (a 0, b 0 ) (a 1, b 1 ) (a 2, b 2 ) (a 3, b 3 ) (a 4, b 4 ) (a 5, b 5 ) (a 6, b 6 ) (a 7, b 7 ) (a 8, b 8 ) (a 9, b 9 ) (a 10, b 10 ) (a 11, b 11 ) (a 12, b 12 ) (a 13, b 13 ) (a 14, b 14 ) (a 15, b 15 ) bit radix-2 sparse tree with sparseness of

13 Tree Adders (A 0, B 0 ) (A 1, B 1 ) (A 2, B 2 ) (A 3, B 3 ) (A 4, B 4 ) (A 5, B 5 ) (A 6, B 6 ) (A 7, B 7 ) (A 8, B 8 ) (A 9, B 9 ) (A 10, B 10 ) (A 11, B 11 ) (A 12, B 12 ) (A 13, B 13 ) (A 14, B 14 ) (A 15, B 15 ) Brent-Kung Tree 25 Example: Domino Adder V DD V DD G i = a i b i P i = a i + b i a i a i b i b i Propagate Generate 26 13

14 Example: Domino Adder V DD V DD k P i:i-2k+1 k G i:i-2k+1 P i:i-k+1 P i:i-k+1 G i:i-k+1 P i-k:i-2k+1 G i-k:i-2k+1 Propagate Generate 27 Example: Domino um V DD V DD Keeper d um Gi:0 i 0 d Gi:0 i

15 Next Lecture Multipliers Other datapath operators 29 Multipliers 30 15

16 The Binary Multiplication Z M+ N 1 X = Y = Z k 2 k k = 0 M 1 X i 2 i N 1 Y j 2 j = i = 0 j = 0 = M 1 i = 0 N 1 j = 0 X i Y j 2 i+ j with X Y = = M 1 X i 2 i i = 0 N 1 Y j 2 j j = 0 31 The Binary Multiplication 32 16

17 The Array Multiplier 33 The MxN Array Multiplier ritical Path HA HA HA ritical Path 1 ritical Path 2 ritical Path 1 & 2 HA 34 17

18 arry-ave Multiplier HA HA HA HA HA HA HA HA Vector Merging Adder 35 Multiplier Floorplan X 3 X 2 X 1 X 0 Y 0 Y 1 Z 0 HA Multiplier ell Multiplier ell Y 2 Z 1 Vector Merging ell Y 3 Z 2 X and Y signals are broadcasted through the complete array. ( ) Z 7 Z 6 Z 5 Z 4 Z

19 Wallace-Tree Multiplier 37 Wallace-Tree Multiplier 38 19

20 Wallace-Tree Multiplier y 0 y 1 y2 i-1 y 0 y 1 y 2 y 3 y 4 y 5 y 3 i i-1 i i i-1 i-1 y 4 i i-1 i i-1 y 5 i 39 Multipliers ummary Optimization Goals Different Vs Binary Adder Once Again: Identify ritical Path Other possible techniques - Logarithmic versus Linear (Wallace Tree Mult) - Data encoding (Booth) - Pipelining FIRT GLIMPE AT YTEM LEVEL OPTIMIZATION 40 20