! Delay when A=1, B=0? ! CMOS Gates. " Dual pull-down and pull-up networks, only one enabled at a time

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1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Pass Transistor XOR Delay when A, B0? Start with equivalent RC circuit Lec : October 9, 08 Driving Large Capacitive Loads 3 Unbuffered Unbuffered Circuit Delay? Circuit Delay? 4 5 Unbuffered Logic Types Delay as a function of number of stages? CMOS Gates Dual pull-down and pull-up networks, only one enabled at a time Performance of gate is strong function of the fanin of gate Techniques to improve performance include sizing, input reordering, and buffering (staging Ratioed Gates Have active pull-down (-up network connected to device Reduced gate complexity at expense of static power asymmetric transfer function Techniques to improve performance include sizing to improve noise margins and reduce static power Pass Gates Implement logic gate as switch network for reduced area and capacitance Long cascades of switches result in quadratic increase in delay Also suffer from reduced noise margins (V T drop Use level-restoring buffers to improve noise margins 6 Penn ESE 370 Fall 08 Khanna Dynamic logic coming up soon 7

2 Today Message Back to CMOS today To drive large s How do we drive a large capacitive? Scale buffers geometrically Stages and buffer sizing Minimum delay Exponential scale up in buffer size Scale factor: 3 4 typically One origin of fanout 4 target Drains contribute capacitance too (C diff Can formulate sizing to optimize 8 9 Call back: Large Fanout Delay Call back: and Again hat is delay if must drive fanout00? Delay here? 0 One Stage Start C diff 0 How do we size to minimize delay? N 3

3 One Stage Delay equation? One Stage Delay equation? delay R 0 N + R 0 N C N N 4 5 Minimize Minimize delay R 0 N + R 0 N C delay R 0 N + R 0 N C Differentiate and set to zero Differentiate and set to zero hat s N? R 0 R 0 N C 0 hat s N? R 0 R 0 N C 0 C N C 6 7 Concrete? k-stage hat is N for C 4x0 4? N C N N N 8 9 3

4 k-stage Delay Size to minimize delay How do we minimize? τ N N C N (k N N τ N N C N (k 0 Size to minimize delay Delay Take partial derivative with respect to and set 0 Conclude: at optimal sizing, ratio of stages is same: τ N N C N (k τ N (i+ ( +... ' 0 N (i+ N (i+ Ni N (i+ N (i+ Ni N (i+ 3 Delay Stage Delay Call that ratio ρ ρ N (i+ τ N N C N (k τ N R ' C N N (k τ ( 4 5 4

5 Stage Delay Stage Delay τ N N C N (k τ N R ' C N N (k τ ( N ρ N N (i+ N N 3 N N N (i+ Ni C N (k ( C ( ρ N N (i+ C ( Two simplifications? in terms of ρ? without ρ? 6 7 Stage Delay Stage Delay ρ N N (i+ C ( ρ k+ C C ρ k+ 4 4 N N N N 3 N N N N 3 N N N (i+ Ni N (i+ Ni N (k N (k C C ( ρ k+ ( C ( ρ C k+ 8 9 Total Delay Total Delay ρ N N (i+ C τ N N C N (k τ N R ' C N N (k τ ( TotalDelay τ (k +ρ ( ρ C k+ TotalDelay τ (k +ρ TotalDelay τ (k + C

6 Plot Delay vs. k (C 4x0 4 Delay (τ units TotalDelay τ (k + C 4 Zoom: Plot Delay vs. k (C 4x0 4 Delay (τ units TotalDelay τ (k + C Stages (k Stages (k 3 33 Minimize Concrete d(b x ln(b bx dx d( x dx x TotalDelay τ (k + C 4 C 0 τ (k + ln C C * + 0 'ln C ' k + 4 k ln C 4,. k hat is optimal k for C 4x0 4? k ln C Zoom: Plot Delay vs. k (C 4x0 4 Optimum Scale Up Delay (τ units TotalDelay τ (k + C For optimum delay k ln C 4 hat is ρ? ρ C k Stages (k

7 Optimum Scale Up ρ C ln(ρ ln C ( Y ln(y ln( Y ρ e ln( Y Call Back: Total Delay ρ N N (i+ C τ N N C N (k τ N R ' C N N (k τ ( TotalDelay τ (k +ρ ( Delay at Optimum Zoom: Plot Delay vs. k (C 4x0 4 k ln C 4 ρ e TotalDelay τ (k + C 4 TotalDelay τ (k +ρ TotalDelay τ ln C ' e 4 Delay (τ units hat is optimal delay for C 4x0 4? Stages (k 4 Diffusion Capacitance C diff γc gate hat does this do to τ model? Delay of middle stage?

8 Diffusion Capacitance (C diff0 γ hat does this do to τ model? Delay of middle stage? delay R 0 ' C diff 0 + delay R 0 '( γ + delay τ γ + ' ( Call back: Total Delay ρ N N (i+ C τ N N C N (k τ N R ' C N N (k τ ( TotalDelay τ (k +ρ ( k-stage Delay k-stage Delay τ N N C N (k delay τ γ + ' τ γ + N +γ + +γ γ + +γ γ + N ' N (k + R 0 (C + γ 46 τ γ + N +γ + +γ γ + +γ γ + N ' N (k τ γk + N N (C + γ N (k τ γk + N N C + τγ N (k τ γk + N R 0 C +γ N N (k τ ' τ γ(k ++ N R C N N (k τ ( ' + R 0 (C + γ 47 Call back: Size to minimize delay Take partial derivative with respect to 0 τ γ(k ++ N R C N N (k τ ( ' τ N (i+ ( +... ' 0 Call back: Delay Call that ratio ρ ρ N (i+ N (i+ N (i+ Ni N (i

9 Impact on Minimum? Partial derivative unchanged τ γ(k ++ N R C N N (k τ ( ' Stage Delay: ρ unchanged (for fixed k ρ N N (i+ ρ C k+ TotalDelay τ (k +(ρ +γ C TotalDelay τ (k + 4 C ( τ γ(k ++ N R C N N (k τ ( ' +γ 5 Impact of Gamma Impact of Gamma Delay (τ units γ.5 γ.0 γ0.5 γ0 Delay (τ units γ.5 γ.0 γ0.5 γ Stages (k Stages (k 5 53 Minimize Solve TotalDelay τ (k +(ρ +γ C TotalDelay τ (k τ γ + C * + (k + ln C C γ + ρ (k + ln C ρ 4 k + γ + ρ ln C ρ 4 k + +γ,. k γ + ρ ln C ρ k + γ ρ + ln C k

10 Solve Optimal Staging Any γ ρ C k+ γ + ρ ln C ρ k + γ ρ + ln C k + γ + ln C ρ γ + ln( ρ ρ k+ 56 ρ e γ ( + ρ 57 ρ and γ? Impact of Gamma ρ4 is optimal for what γ? ρ3 is optimal for what γ? ρ e γ ( + ρ Delay (τ units γ.5 γ.0 γ0.5 γ Stages (k Optimal Fanout Idea Clearer why we use ρ4 as our benchmark? To drive large s Scale buffers geometrically Exponential scale up in buffer size (ρ e Scale factor: 3 4 typically One origin of fanout 4 target Drains contribute capacitance, too (C diff Can formulate sizing to optimize 6 0

11 Admin Project due Thursday at :59pm Tania office hours Monday -:30pm and ednesday -3pm Angelina office hours Tuesday 6-8pm Reminder: Midterm on Monday next week Notify me with conflicts ASAP 6