EE141-Fall 2012 Digital Integrated Circuits. Announcements. Homework #3 due today. Homework #4 due next Thursday EECS141 EE141

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1 EE4-Fall 0 Digital Integrated Circuits Lecture 7 Gate Delay and Logical Effort nnouncements Homework #3 due today Homework #4 due next Thursday

2 Class Material Last lecture Inverter delay optimization Today s lecture Gate delay and logical effort Reading (Chapter 6) 3 Complex Gate Delay Use RC model to estimate delay: R p R p R n C L R n Cint 4

3 Complex Gate Delay () Now what is the delay? R p R p R n C L R n Cint 5 Elmore Delay Elmore delay : approximation for delay of arbitrary (complex) RC circuits To find Elmore time constant : For each capacitor, draw path of current from cap to input Multiply C by sum of R s on current path that are common with path from V in to V out dd up RC products from all capacitors 6 3

4 Elmore Delay (Formal Method) Set V in to (incremental) ground pply current I across C, measure V out Calculate R eff = V out /I Time constant due to that C is R eff *C 7 Simplified Model: Elmore Delay Elmore R C R R C R R R C

5 nother Elmore Delay Example R V in R 3 V out C R C C 3 Elmore 9 nother Example Gate 0 5

6 Gate Sizing R p R p 4 R p R n C L 4 R p C int R n Cint R n R n C L Sizing Example C D D OUT = D + ( + C) C 6

7 Logical Effort 3 Question # ll of these are decoders Which one is best? 4 7

8 Question # Is it better to drive a big capacitive load directly with the NND gate, or after some buffering? C L C L Method to answer both of these questions: Logical effort Extension of buffer sizing problem 5 uffer Chain Review In Out C C C N N C L = C N+ Delay t f N inv i i For given N: C i+ /C i = C i /C i- To find N: C i+ /C i ~ 4 f i = C i+ /C i 6 8

9 Delay of NND Gate C dnand = 6C D Cgnand = 4C G = (4/3) C ginv C D /C G = t pnnd = kr W (C int + C L) = k(r sq,n *L/W)(WC dnand + C L ) = k(r sq,n *L*C gnand )(C dnand /C gnand +C L /(WC gnand )) = k(r sq,n *L*4*C g )(3/* +C L /(WC gnand )) = (4/3) t inv (3/ + f) 7 Delay of NOR Gate 4 C dnor = 6C D Cgnor = 5C G = (5/3) C ginv C D /C G = 4 t pnnd = kr(c int + C L) = k(r sq,n *L/W)(WC dnor + C L ) = k(r sq,n *L*C gnor )(C dnor /C gnor +C L /(WC gnor )) = k(r sq,n *L*5*C g )(6/5* +C L /(WC gnor )) = (5/3) t inv (6/5 + f) 8 9

10 Sizing a Chain t p,tot = t inv [C nd /C inv ) + 4/3*(3/*+C nr /C nd ) + 5/3*(6/5*+C L /C nr )] = t inv [( + C nd /C inv ) + ( + (4/3)*C nr /C nd ) + ( + (5/3)*C L /C nr )] You already know how to solve this! NND and NOR are just like inverters Except that their fanout looks larger i.e., get more delay than an inverter for same fanout 9 Logical Effort t p,tot = t inv [C nd /C inv ) + 4/3*(3/*+C nr /C nd ) + 5/3*(6/5*+C L /C nr )] = t inv [( + C nd /C inv ) + ( + (4/3)*C nr /C nd ) + ( + (5/3)*C L /C nr )] p gate parasitic delay f(w) LE logical effort f(w) f electrical fanout t pgate = t inv (p gate + LE f) 0 0

11 Finding Logical Effort of a Gate Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates So normalize everything to inverter Logical effort LE is defined as: (R eq,gate C in,gate )/(R eq,inv C in,inv ) Easiest way to calculate (usually): Size gate to deliver same current as an inverter, take ratio of gate input capacitance to inverter capacitance LE increases with gate complexity Finding Logical Effort of a Gate Calculating LE by sizing for same drive strength: V DD V DD V DD 4 F F 4 F Inverter -input NND -input NOR LE = LE = LE =

12 Gate Sizing Convention Need to set a convention: What does a gate of size mean? For an inverter it is clear: C inv =, R inv = ½ For a gate, two possibilities: C gate = C inv R gate = (LE/)*R inv R gate = R inv / C gate = (*LE)*C inv In my notes, size C gate /C inv Size gate has twice the input capacitance of a unit inverter 3 dding ranching ranching effort: C b C L, onpath L, off path C Lon, path C L,on_path C L,off_path 4

13 Chain of rbitrary Gates N i Delay p LE f i i i Effective fanout: EF i = LE i f i Path electrical fanout: F = C out /C in Path logical effort: LE = LE LE LE N ranching effort: = b b b N Path effort: PE = LE F Path delay D = d i = p i + EF i 5 Optimum EF/Stage Just like buffer chain, but use (PE, EF) instead of (F, f): N EF EF PE N PE Effective fanouts: LE f = LE f = = LE N f N Minimum path delay / N ˆ N N i i i i i i D LE f p N PE p 6 3

14 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing / N D NPE p i Remember: we can always add inverters to the end of the chain The best effective fanout EF PE / Nˆ is still around 4 (3.6 with =) 7 Example: Optimize Path a b c 5 LE = f = a LE = 5/3 f = b/a LE = 5/3 f = c/b LE = f = 5/c Electrical fanout, F = LE = PE = EF/stage = a = b = c = 8 4

15 Example: Optimize Path a b c 5 LE = f = a LE = 5/3 f = b/a LE = 5/3 f = c/b LE = f = 5/c Electrical fanout, F = 5 LE = (5/3) (5/3) = (5/9) PE = ( LE) F = (5/9) EF/stage = (5/9)^(/4) =.93 a =.93 b =.3 c =.59 5/c =.93 (5/3)c/b =.93 (5/3)b/a =.93 9 Method of Logical Effort Compute the path effort: PE = (LE)F Find the best number of stages N ~ log 4 PE Compute the effective fanout/stage EF = PE /N Sketch the path with this number of stages Work either from either end, find sizes: C in = C out *LE/EF Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann

16 Next Lecture pplying logical effort to a decoder 3 6

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