Digital Microelectronic Circuits ( )


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1 Digital Microelectronic ircuits ( ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1
2 Motivation Thus far, we have learned how to model our essential building block, the MOSFET transistor, and how to use these building blocks to create the most popular logic family, Static MOS. We analyzed the characteristics of a static MOS inverter, including its Static and Dynamic Properties. We saw that both the delay and the power consumption of a MOS gate depend on the load capacitance of the gate. t 0.69R P f V 2 pd eq Load dynamic DD 2
3 What will we learn today? Today, we will go back to our MOSFET transistor to try and understand what parasitic capacitances are inherent to its structure. Then, we will develop a model for equivalent capacitance estimation for delay calculation of a MOS inverter. Accordingly, we will examine the optimal sizing of a MOS gate. And finally, we will develop a methodology for sizing a chain of inverters to drive a large load. 3
4 What will we learn today? 5.1 MOSFET apacitance 5.2 Inverter Delay apacitance Model 5.3 Driving a Load 4
5 MOSFET apacitance 5.2 Inverter Delay apacitance Model 5.3 Driving a Load So back to our device, let s see what parasitic capacitances we have: MOSFET APAITANE 5
6 MOSFET apacitance One of the important parameters of a MOS Transistor is its capacitance. The MOSFET has two major categories of capacitance:» Gate/hannel apacitance capacitance caused by the insulating oxide layer under the gate.» Junction apacitance pnjunction capacitance between the diffusions and the substrate. t ox GS GD n + L n + G SB psubstrate DB 6
7 Gate apacitance The Gate apacitance includes:» Gate to hannel apacitance, G : The main capacitance that is dependent on the region of operation. In general: ox G WL oxwl tox» Gate Overlap apacitance, GDO, GSO : A constant (small) capacitance caused by gate overlap of the diffusions. W GSO GDO Overlap 7
8 Gate apacitance Looking at gate capacitance as a function of biasing shows how it changes.» In accumulation, the capacitance is across the oxide.» As V GS grows, the depletion layer decreases the capacitance (as if the dielectric gets longer)» Once the channel is formed, the capacitance jumps.» At pinchoff, the drain capacitance drops to zero. 8
9 Gate apacitance 9
10 Gate apacitance To model this nonlinear behavior, we will use the following approximations: All capacitance is towards substrate GB WL ox apacitance symmetrically divided between source and drain GS GD WL ox 2 All capacitance to Source Question: How do we relate to Velocity Saturation? GS 2 3 WL ox 10
11 Junction (Diffusion) apacitance The Junction apacitance is the diffusion capacitance of the MOSFET. This is measured according to fabrication parameters diff bottom side walls Area Perimiter j jsw L W 2L W j diff jsw diff Diffusion cap is nonlinear and voltage dependent. For simplicity, we will take it as constant in this course. 11
12 MOSFET apacitance Summary Dependence of MOS capacitances on W and L: 12
13 MOSFET apacitance Summary G GS GD GS GS GSO S D GD GD GDO GB GB SB GB DB SB Sdiff DB Ddiff B 13
14 MOSFET apacitance 5.2 Inverter Delay apacitance Model 5.3 Driving a Load OK, so we saw that the MOSFET has a bunch of nonlinear parasitic capacitances, which makes them tough to use. To simplify life we ll now develop an: INVERTER DELAY APAITANE MODEL 14
15 apacitance Modeling As we saw, MOSFET capacitances are nonconstant and nonlinear. Therefore, it is hard to solve a general equation for an arbitrary transition/operation. Instead, we will develop a simple model that will approximate the capacitances during a specific transition that interests us. In this case, we are looking for the Load apacitance to use when finding the gate delay. Therefore, we will apply a step function to the input of an inverter and approximate the capacitances according to the MOSFET parasitics we just learned. 15
16 apacitance Modeling Let s look at a MOS inverter with all its parasitic capacitances:» onsidering the Gates of the transistors are the inputs to the inverter, any capacitor touching the gate should be considered input capacitance. V in» onsidering the Drains of the transistors are connected to the inverter output, any capacitor touching the Drains should be considered output capacitance. G GDP GSP GDN G GSN B GBN S GBP D D B S SBP DBP V out DBN SBN 16
17 apacitance Modeling We have to differentiate between output (intrinsic) capacitances and load (extrinsic) capacitances. Driver Load wire out,1 in,2 int ext Our total load capacitance is Load out,1 wire in,2 17
18 Intrinsic (Output) apacitance We ll now look at what makes up the intrinsic output capacitance of the driver. This is primarily made up of diffusion capacitances:» Both draintobody capacitances have a terminal with a constant voltage and the other connected to the output.» For a simple computation, we will replace them with an equivalent capacitance to ground.» These capacitances are very nonlinear and we will not go into their calculation in this course. DBP DBP + DBN DBN 18
19 Intrinsic (Output) apacitance How about feedthrough capacitance?» Taking the input step as ideal, the gatetosource and gatetobody capacitances don t contribute to the propagation delay.» The sourcetobody capacitance is shorted to the supply, so it doesn t switch. GSP + GBP GDP + GDN What about the gatetodrain capacitance?» While the gate voltage rises (V in ), the drain voltage drops (V out ) and vice versa.» According to the Miller Effect, we can move this capacitance relative to ground, doubling its value.» This can be regarded as overlap capacitance, as for the majority of the transition the devices are in cutoff or saturation. GSN + GBN 2( GDP + GDN ) 19
20 The Miller Effect A capacitor experiencing identical, but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is twice the original value. 20
21 Summary of Intrinsic Output ap 21
22 External apacitance Now, to annotate the parasitics during switching, we will cascade another inverter after the first. We first add the Wire apacitance. Then we add the gate capacitances of the second inverter.» These are approximately the oxide capacitance times the area: W L W L GN 2 GP2 OX N 2 N 2 P2 P2» Again, we can just add the pmos gate capacitance to the general capacitance to ground. P1 N1 W GP2 GN2 P2 N2 22
23 External apacitance What happened to overlap capacitance and the Miller Effect on GD2?» Remember that this is an approximate model, but» L=L eff +2*L ov, so G = ox *W*L drawn.» During the transient, for most of the time the load gate s transistors are in cutoff or in linear.» Miller effect won t appear, because the second gate won t switch until t pd1 is over. Therefore:» YES, GD2 and GS2 contribute to the load capacitance.» BUT, a good approximation is just G2 = OX *W*L 23
24 Summary of Next Stage Input ap 24
25 Parasitic apacitances  Summary Altogether, as a very general approximation, we get: 2( ) load GDP1 GDN 1 DBP1 DBN 1 GP2 GN 2 W Miller Diffusion Load GP2 An even more general approximation with N fanout gates gives us: load out wire N in GDP1 + GDN1 P1 DBP1 P2 N1 DBN1 + W N2 GN2 25
26 Last Time MOS Inverter apacitance Model for t pd. 26
27 Last Time MOS apacitance Model» Driver ap ( out or int ): Diffusion + Miller» Load ap ( in or g ): Gate cap, no miller N load out wire in 27
28 MOSFET apacitance 5.2 Inverter Delay apacitance Model 5.3 Driving a Load Up till now, we discussed device sizing with an optimal fanout of 1. What happens if we want to cascade more gates to the output? DRIVING A LOAD 28
29 External apacitance Up till now, we assumed our inverter was only driving a copy of itself. This is known as intrinsic or unloaded delay. But we usually will have a larger fanout, and in some cases, we will need to drive large loads. Let s remember how we defined our load capacitance: load diff overlap fanout wire int ext We can now write our delay equation according to these components. t 0.69R 0.69R pd eq load eq int ext Driver out,1 int ext Load wire in,2 29
30 Sizing Factor (S) t 0.69R pd eq int ext This means that if we add a larger load, our delay will increase. This is intuitive, as it means we have to supply more current from the same source. If we were to widen our transistors by a factor S, this would decrease our resistance and increase our intrinsic * * capacitance. S R R S int int eq eq 30
31 S R R S * * int int eq eq Sizing Factor (S) t 0.69R pd eq int ext These two factors tradeoff, which is why we get an optimal inverter size. * * * Req tpd unloaded 0.69Req 0.69 S 0.69Req S, int int int However, upsizing our gate doesn t affect the external capacitance and therefore decreases the loaded delay. R * eq ext ext t pd 0.69 Sint ext 0.69Req int 1 t p0 1 S Sint Sint 31
32 Sizing Factor (S) t t p t p R ext p0 eq int S int 32
33 Driving a Large Load So now we have a very large load to drive. We could just use a very large inverter.» But then someone would have to drive this large inverter. So considering we start with a limited input capacitance, how should we best drive this load? 34
34 Inverter hain In Out L If L is given:» How many stages are needed to minimize the delay?» How to size the inverters? Anyone want to guess the solution? 35
35 Delay Optimization Problem #1 To solve an optimization problem, we need a set of constraints:» Load apacitance.» Number of Inverters.» Size of input capacitance. 36
36 Delay Optimization Problem #1 To explore this problem, we must define a proportionality factor, γ. γ is a function of technology*, that describes the relationship between a gate s input gate capacitance ( g ) and its intrinsic output capacitance ( int ): int * γ is close to 1 for most submicron processes! g 37
37 Delay Optimization Problem #1 Now, we will write the delay as a function of γ, and the effective fanout, f: ext f t pd t p0 1 t p01 f g int ext g g We can see that the delay for a certain technology is only a function of the effective fanout! 38
38 Inverter with Load So we see that the delay increases with ratio of load to inverter size: t t p p0 1 f t p0 is the intrinsic delay of an unloaded inverter. γ is a technology dependent ratio. f is the Effective Fanout ratio of load to inverter size 39
39 Sizing a chain of inverters Now we will express the delay of a chain of inverters: t t p p0 1 f Assuming a negligible wire capacitance, for the jth stage, we get: f t t t j g, j1 pd, j p0 1 p0 1 g, j And we can write the total delay as: N N g, j1 pd pd, j p0 1 j1 j1 g, j t t t 40
40 Sizing a chain of inverters We have N1 unknowns, so we will derive N1 partial derivatives: t g, j We receive a set of constraints: pd 0 t pd t p0 N 1 g, j1 j 1 g, j g, j1 g, j g, j g, j1 This means that: g, j g, j 1 g, j 1» Each inverter is sized up by the same factor, f.» Each inverter has the same effective fanout, f j =f.» Each inverter has the same delay, t p0 (1+f/ γ). 41
41 Sizing a chain of inverters Now this is interesting what if we multiply the fanout of each stage?: f N N N g, j1 g,2 g,3 g,4 g, N load load f j j1 j1 g, j g,1 g,2 g,3 g, N 1 g, N g,1 We found the ratio between input and load capacitance! f N / F load g,1 N F load g,1 42
42 Sizing a chain of inverters f N F g,1 We defined the overall effective fanout, F, between the input and load capacitance of the circuit. Using this parameter, we can express the total delay: t pd N t p0 1 N F F load 43
43 Example: 3 Stages In S=1 S=2 S=4 Out 1 1 f f 2 L = 8 1 L / 1 has to be evenly distributed across N = 3 stages: f
44 Delay Optimization Problem #2 Great but what is the optimal Number of Stages? This is a new Optimization Problem. You are given:» The size of the first inverter» The size of the load that needs to be driven Your goal:» Minimize delay by finding optimal number and sizes of gates So, need to find N that minimizes: t p N t p0 1 N F 45
45 Delay Optimization Problem #2 Starting with a minimum sized inverter with g,min, and driving a given load, load, we can see that:» With a small number of stages, we get a large delay due to the effective fanout (f, F).» With a large number of stages, we get a large delay due to the intrinsic delay (Nt p0 ) t pd N t p0 1 N F To find the optimal number of stages, we will differentiate and equate to zero. dt pd dn 0 N N F ln F F 0 fopt exp1 N f opt 46
46 Delay Optimization Problem #2 This equation only has an analytical solution for the case of γ=0. In this esoteric case we get: f opt exp 1 f opt fopt e Nopt 0 ln F If we take the typical case of γ=1, we can numerically solve the equation and arrive at: f opt 3.6 N log opt F 47
47 We are given: We need to find the optimal number of stages, so f opt =4. F N opt L in 64 L in 4 64 Example min log F log 64 3 f opt min So we need 3 stages that will be sized 1, 4, 16. Let s inspect what delay we would have gotten with various number of stages. 48
48 Example t pd N t p0 1 N F N f t p
49 Normalized delay function of F Let s consider the trade offs of driving loads with various approaches:» Unbuffered» TwoStages» Optimal FO4 hain t pd N t p0 1 N F For a small load, F=10:» Unbuffered delay: t pd =11t p0» Two Stage delay: t pd =8.3t p0» Optimal FO4 hain: N opt =2t pd =8.3t p0 50
50 Normalized delay function of F For a slightly larger load, F=100:» Unbuffered delay: t pd =101t p0» Two Stage delay: t pd =22t p0» Optimal FO4 hain: N opt =4 t pd =16.6t p0» We see a large benefit for one extra stage, but the inverter chain might not be worth it. How about a really large load, F=10000:» Unbuffered delay: t pd =10001t p0» Two Stage delay: t pd =202t p0 t pd N t p0 1 N F» Optimal FO4 hain: N opt =7 t pd =33.1t p0» But we pay for this with a large number of stages and huge final stage inverter (W=1mm) 51
51 What about Energy (and Area)? How much additional Energy (and Area) does an inverter chain cost?» Using a single (minimal) inverter, our capacitance would be: 1 stage min min L» But the capacitance of N stages 1 1 f... 1 f N 1 N stages min min min L 1 f... 1 f N 1 1stage min min Overhead! 52
52 What about Energy (and Area)? So the overhead cap is: 1 f 1 f... f overhead N 2 min N fmin f f For example: L 20 pf, min 50 ff 20 pf 5 F 400, Nopt 5, f ff overhead pf 4 53
53 Example Overhead Numbers For the previous example: 54
54 onclusions In order to drive a large load, we should:» Use a chain of inverters.» Each inverter should increase its size by the same amount.» To minimize the delay, we should set the effective fanout to about 4. Remember!» You have to use a whole number of stages (i.e. you can t choose 2.5 stages).» Therefore, choose the closest number of stages for close to optimal effective fanout..» hoose according to signal polarity or optimal speed.» But fewer stages means less power! 55
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