Dynamic Combinational Circuits. Dynamic Logic

Transcription

1 Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes: precharge and evaluate Krish Chakrabarty 2 1

2 The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. Krish Chakrabarty 3 Dynamic Logic I n 1 I n 2 I n 3 P D N C L I n 1 I n 2 I n 3 P U N C L n network P r e c h a r g e p network 2 p h a s e o p e r a t i o n : E v a l u a t i o n Krish Chakrabarty 4 2

3 Logical Effort Krish Chakrabarty 5 Dynamic Logic N+2 transistors for N-input function Better than 2N transistors for complementary static CMOS Comparable to N+1 for ratio-ed logic No static power dissipation Better than ratio-ed logic Careful design, clock signal needed Krish Chakrabarty 6 3

4 Dynamic Logic: Principles Precharge = 0, Out is precharged to V DD by M p. M e is turned off, no dc current flows (regardless of input values) I n 1 I n 2 I n 3 P D N C L Evaluation = 1, M e is turned on, M p is turned off. Output is pulled down to zero depending on the values on the inputs. If not, precharged value remains on C L. Important: Once Out is discharged, it cannot be charged again! Gate input can make only one transition during evaluation Minimum clock frequency must be maintained Can M e be eliminated? Krish Chakrabarty 7 Example R a t i o l e s s N o S t a t i c P o w e r C o n s u m p t i o n A B C N o i s e M a r g i n s s m a l l ( N M L ) R e q u i r e s C l o c k Krish Chakrabarty 8 4

5 Dynamic 4 Input NAND Gate V DD Out In 1 In 2 In 3 In 4 GND Krish Chakrabarty 9 Cascading Dynamic Gates V 1 2 I n I n 1 V T n 2 t Internal nodes can only make 0-1 transitions during evaluation period Krish Chakrabarty 10 5

6 Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 0 -> 1 1 -> 1 But not 1 -> 0 Krish Chakrabarty 11 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! Krish Chakrabarty 12 6

7 Reliability Problems Charge Leakage A ( 1 ) ( 2 ) C L V o u t p r e c h a r g e e v a l u a t e t A = 0 ( a ) L e a k a g e s o u r c e s ( b ) E f f e c t o n w a v e f o r m s t (1) Leakage through reverse-biased diode of the diffusion area (2) Subthreshold current from drain to source M i n i m u m C l o c k F r e q u e n c y : > 1 M H z Krish Chakrabarty 13 Leakage Dynamic node floats high during evaluation Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation Krish Chakrabarty 14 7

8 Charge Sharing (redistribution) Assume: during precharge, A and B are 0, C a is discharged During evaluation, B remains 0 and A rises to 1 Charge stored on C L is now redistributed over C L and C a A B = 0 M a X M b C a C L C L V DD = C L V out (t) + C a V X V X = V DD - V t, therefore V out (t) = V out (t) - V DD = C a (V DD -V t ) C L C b Desirable to keep the voltage drop below threshold of pmos transistor (why?) C a /C L < 0.2 Krish Chakrabarty 15 Charge Sharing Dynamic gates suffer from charge sharing Krish Chakrabarty 16 8

9 Charge Redistribution - Solutions M b l M b l A M a A M a B M b B M b ( a ) S t a t i c b l e e d e r ( b ) P r e c h a r g e o f i n t e r n a l n o d e s Krish Chakrabarty 17 Secondary Precharge Solution: add secondary precharge transistors Typically need to precharge every other node Big load capacitance C Y helps as well Krish Chakrabarty 18 9

10 Domino Logic 1 M r 2 I n 1 I n 2 I n 3 P D N I n 4 P D N S t a t i c I n v e r t e r w i t h L e v e l R e s t o r e r Static inverters between dynamic stages Krish Chakrabarty 19 Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Krish Chakrabarty 20 10

11 Domino Logic - Characteristics O n l y n o n - i n v e r t i n g l o g i c V e r y f a s t - O n l y 1 - > 0 t r a n s i t i o n s a t i n p u t o f i n v e r t e r Precharging makes pull-up very fast A d d i n g l e v e l r e s t o r e r r e d u c e s l e a k a g e a n d c h a r g e r e d i s t r i b u t i o n p r o b l e m s O p t i m i z e i n v e r t e r f o r f a n - o u t Krish Chakrabarty 21 Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic Krish Chakrabarty 22 11

12 Dual-Rail Domino Domino only performs noninverting functions: AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged invalid Krish Chakrabarty 23 Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements Krish Chakrabarty 24 12

13 Example: XOR/XNOR Sometimes possible to share transistors Krish Chakrabarty 25 Domino Summary Domino logic is attractive for high-speed circuits 1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in high-performance microprocessors Krish Chakrabarty 26 13

14 np-cmos (Zipper CMOS) 1 I n 1 I n 2 I n 3 P D N I n 4 P U N 2 Only 1-0 transitions allowed at inputs of PUN Used a lot in the Alpha design Krish Chakrabarty 27 np CMOS Adder Krish Chakrabarty 28 14

15 CMOS Circuit Styles - Summary Krish Chakrabarty 29 15