Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.


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1 ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler Paths! Energy asics & Optimization 2 Restore Output Pass Transistor Logic 4 Voltage of hain How compare! What is voltage at output? V dd =1V V thn =V thp =0.3V! ompare 5 6 1
2 nalysis chain of 3 nalysis chain of onclude Transient! an chain any number of pass transistors and only drop a single V th 9 10 Transient: Zoomed loseup Gate ascade?! What are voltages? V dd =1V V thn =V thp =0.3V
3 hain Together ascaded Pass Gates elay =1, =0, = diff = d? elay =1, =0, = diff = d?! What s the equivalent R circuit?! What s the equivalent R circuit? " What is the total delay? " rom to Y 2 g 2 g 3 d 2 d +2 g 3 d 2 d +2 g elay =1, =1, = diff = d? ascading Pass Gates! What s the equivalent R circuit? one stage /b /c /d y b /y c d 2 g /b /c /d 17 Penn ESE 3570 Spring Khanna 18 3
4 hain without Inverters! Extract key path /a a 19 Logic Types! MOS Gates " ual pulldown and pullup networks, only one enabled at a time " Performance of gate is strong function of the fanin of gate " Techniques to improve performance include sizing, input reordering, and buffering (staging)! Ratioed Gates " Have active pulldown (up) network connected to load device " Reduced gate complexity at expense of static power asymmetric transfer function " Techniques to improve performance include sizing to improve noise margins and reduce static power! Pass Gates " Implement logic gate as switch network for reduced area and load capacitance " Long cascades of switches result in quadratic increase in delay " lso suffer from reduced noise margins (V T drop) " Use levelrestoring buffers to improve noise margins! ynamic logic coming up soon 20 Transmission Gates MOS Transmission Gates LK LK 22 MOS Transmission Gates MOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V
5 MOS Transmission Gates MOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V  V Tp 25  V Tp 26 MOS Transmission Gates MOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V  V Tp 27  V Tp 28 Transmission Gate, R eq Transmission Gate, R eq k p ( V  V Tp ) 2 k p [2( V  V tp ) (V out V )  (V out V ) 2 ] k p [2( V  V tp )  (V out V )] k p [2( V  V tp )  (V out V )]
6 Transmission Gate, R eq Transmission Gate Layouts Transmission Gate Layouts Euler Paths 33 NOR2 Layout NN2 Layout
7 Layout of omplex MOS Gate Layout of omplex MOS Gate S S GN Layout of omplex MOS Gate Minimize Number of iffusion Paths diffusion breaks d d d d d i.e. n, p Euler paths with identical sequences of inputs Minimize Number of iffusion Paths Minimize Number of iffusion Paths
8 Minimize Number of iffusion Paths Gate Layout lgorithm! 1. ind all Euler paths that cover the graph! 2. ind common n and p Euler paths! 3. If no common n and p Euler paths are found in step 2, partition the gate n and p graphs into the minimum number of subgraphs that will result in separate common n and p Euler paths Total Power Energy and Power asics! P tot P static + P dyn + P sc Review 46 Operating Modes Static Leakage Power! SteadyState: V in =V dd " PMOS: subthreshold " NMOS: resistive $ I Sp = I S # W ' & ) e & % % L ( $ V GS V T nkt / q ' $ $ V S '' ) & ) ( 1 e % kt / q ( & ) 1 λv S % ( ( )! W $ ( I Sn = µ n OX # & ( V GS V T )V S V 2 + S *  " L %) 2,
9 Static Power Ratioed Logic! I static?! Input lowoutput high? " I leak Static Power Ratioed Logic! I static?! Input lowoutput high? " I leak! Input highoutput low? " I pmos_on " ~V dd /R p,on Total Static Power! P statit p(v out =low)v 2 /R p,on +p(v out =high)vi s (W/L)eVt/(nkT/q) Switching p(v out =low) probability the output is low p(v out =high) probability the output is high ynamic Power p(v out =high)=1p(v out =low) Switching urrents Switching Energy! I switch (t) = I sc (t) + I dyn (t)! o we know what this is? I sc I sw I dyn! What is Q? E = Q = P(t)dt = I(t)V dd dt = V dd I(t)dt I dyn (t)dt Q = V = E = V dd 2 I(t)dt apacitor charging energy I dyn
10 Switching Power! Every time output switches 0#1 pay: " E = V 2 Switching! P dyn = (# 0#1 trans) V 2 / time Short ircuit Power! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½V 2 / time Short ircuit Power Short ircuit Power! etween V TN and V dd  V TP " oth N and P devices conducting! etween V TN and V dd  V TP " oth N and P devices conducting! Roughly: I sc Vin VddVthp Vthn Vdd time Vdd Isc 57 Vout tsc tsc time 58 Peak urrent! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall % I S ν sat OX W V GS V T V ( ST ' * & 2 ) I(t)dt I t % ' 1( peak sc 2 * & ) # E = V dd I peak t sc % 1& ( Vin $ 2' Vdd VddVthp Vthn time Vdd Isc Short ircuit Energy! Make it look like a capacitance, S " Q=I t " Q=V " " E = V dd I peak t sc 1 %% $ $ '' # # 2 && E = V dd Q S E = V dd ( S V dd ) = S V 2 dd Vout tsc tsc time
11 Short ircuit Energy! Every time switch " lso dissipate shortcircuit energy: E = V 2 " ifferent = sc " cs fake capacitance (for accounting) Short ircuit Energy! When transistors switch, both nmos and pmos networks may be nanotarily ON at once! Leads to a blip of short circuit current! < 10% of dynamic power if rise/fall times are comparable for input and output! We will generally ignore this component in hand analysis, but simulated measured results include it Switching Waveforms Switching Waveforms Switching Power harging Power! Every time output switches 0#1 pay: " E = V 2! P dyn = (# 0#1 trans) V 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½V 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle " requency f = 1/clockperiod! P dyn = (#trans/clock) ½V 2 f! P dyn = (# trans) ½V 2 / time
12 harging Power Switching Power! P dyn = (# 0#1 trans) V 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle! P dyn = (#0#1 trans/clock) V 2 f! Let a = activity factor a = average #tran 0#1 /clock " requency f = 1/clockperiod! P dyn = (# 0#1 trans/clock) V 2 f! P dyn = av 2 f ctivity actor ctivity actor! Let a = activity factor! Let a = activity factor " a = average #tran 0#1 /clock " a = average #tran 0#1 /clock a = p(out i = 0) p(out i+1 =1) a = p(out i = 0)p(out i+1 =1) a = N N N 2 = N 0 (2N N 0 ) N 2 2N a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N Reduce ynamic Power? Reduce ctivity actor! P dyn = av 2 f Tree hain! How do we reduce dynamic power? a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N
13 Reduce ctivity actor Reduce ctivity actor Tree hain Tree hain a = p(out i = 0)p(out i+1 =1) 15/256 a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N Reduce ctivity actor Reduce ctivity actor Tree hain Tree hain a = p(out i = 0)p(out i+1 =1) 7/64 15/256 15/256 a = p(out i = 0)p(out i+1 =1) 7/64 15/256 a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N a = N 0 N 1 2 N 2 = N 0(2 N N 0 ) N 2 2 N Total Power! P tot = P static + P sc + P dyn! P sw = P dyn + P sc a( load V 2 f)! P tot a( load V 2 f) + VI s (W/L)eVt/(nkT/q) Idea! MOS " esign for worst case input switching case and delay! There are other logic disciplines " Ratioed logic " an use pass transistors for logic " Transmission gates " Will see in use in dynamic logic! Let a = activity factor a = average #tran 0#1 /clock
14 Midterm Exam Midterm Topics List! Midterm 3/21 " uring class; starts at exactly 1:30pm, ends at exactly 2:50pm (80 minutes) " Location: ollege Hall 200 " Old exams posted on old course websites " overs Lec inclass worksheet " losed book, no notes or cheat sheets " alculators allowed and recommended, no smart phones! Identify MOS/non MOS! ny logic function $# MOS gate! Noise Margins! ircuit first order switching rise/fall times " Output equivalent resistance " Load capacitance! Transistor " Regions of operation " Parasitic apacitance Model! Layout and stick diagrams! Sizing! 1 st order delay " Worst case " Elmore delay! Ratioed logic 79! Pass logic 80 14
! Energy Optimization. ! Design Space Exploration. " Example. ! P tot P static + P dyn + P sc. ! SteadyState: V in =V dd. " PMOS: subthreshold
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