Chapter 3-7. An Exercise. Problem 1. Digital IC-Design. Problem. Problem. 1, draw the static transistor schematic for the function Q = (A+BC)D
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1 igital I-esign Problem Parameters rom a.35 um process hapter 3-7 n Exercise, draw the static transistor schematic or the unction (+), ind the corresponding domino gate using a PN net 3, ind the Euler path or the PN and draw the layout capacitances or the PN. ssume that the circuit is precharged to 3. Neglect the wire capacitances 5, determine the output voltage in the evaluation phase. ssume worst case charge sharing between the precharged node and the internal nodes in the PN Problem Parameters rom a.35 um process Problem 6, suggest a solution to the charge sharing problem 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor 8, determine the power-delay product or the irst stage. etermine the power consumption i the operating requency is 5 MHz 9, determine the threshold point M or the inverter stage, draw the static transistor schematic or the unction Q (+) The unction is non-inverting, i.e. a two stage operation. Make the inverse unction o Q ollowed by an inverter. The PN or the irst stage is Q ( + ). and are placed in series and both are in parallel with. is placed in series with the other. The PUN is ound by e Morgan law s or by duality i.e. serial connections in PN corresponds to parallel in the PUN and vice versa.
2 Static Gate omino ogic, draw the static transistor schematic or the unction Q (+), ind the corresponding domino gate using a PN net (+) PN omino ogic Euler Path, ind the corresponding domino gate using a PN net 3, ind the Euler path or the PN and draw the layout (+) (+) (+) Static gate
3 Euler Path and ayout Parasitic apacitances 3, ind the Euler path or the PN and draw the layout capacitances in the PN. ssume that the circuit is precharged to 3. Neglect the wire capacitances. (+) Euler Path 3 (+) 3 Note: the path goes through the ground GN GN apacitance capacitances in the PN. Overlap apacitance Gate consists o: Source rain Overlap in the,, and Φ p-transistor iusion in n- and p- drain areas G o W GS o W GS W G hannel & Overlap in the inverter Wire is neglected GN G is a constant per unit length in F/um 3
4 The Miller Eect Parameters.35um Δ I gd is modeled rom out to GN, the value shall be doubled gd Δ Δ gd W Δ gd Electrical Parameters apacitances k n 75 m/ ox 4.6 F/mm Tn.5 ( gd gs ). F/mm (.35mm).3 mm jn.93 F/mm W (.6mm).55 mm jp.4 F/mm γ n.58 / jswn.8 F/mm λ n.5 / k p -6 m/ jswp.38 F/mm Tp (.35mm).38 mm W (.6mm).55 mm γ p -.5 / λ p -.5 / elocity Saturation STn.8 STp -.3 Overlap ap. gd capacitances in the PN. Junction apacitance GN -> / or -> / transition is assumed (to 5% point) rain/source iusion ottom i ot + SW 3 ( W) gd F 6(.. μm) μm 6.6 F G Gate Towards hannel W on t count the wall towards the channel GN s Side Wall 4
5 Junction apacitance capacitances in the PN. etermine K eq : Example K + K P n eqn n j eqswn n jsw High-to-low transition ( to /) NMOS, ottom plate etermine K eq (see eq 5.4) p m.5;.9 ; 3 ;.5 High ow K eq (( ) ( ) High ow ) ( )( m) m m m High ow Transition to 5% point Note: Reverse biased voltages (diodes) i.e. negative voltages n GN K eq (( High) ( ow) ) m m m ( )( m ) High ow ( ) (.9 + 3) (.9 +.5) ( 3+.5)(.5).54 etermine K eq Junction apacitance capacitances in the PN. NMOS,.35 um technology, 3 High-to-low ottom plate K eqn.54 High-to-low Sidewall K eqswn.58 ow-to-high ottom plate K eqn.76 ow-to-high Sidewall K eqswn.78 NMOS I high-to-low transition: n Keqn nj n + Keqswn Pnjswn F j PMOS,.35 um technology, 3 High-to-low ottom plate K eqp.77 High-to-low Sidewall K eqswp.84 rea um Sidewall um ow-to-high ottom plate K eqp.55 ow-to-high Sidewall K eqswp.67 GN 5
6 Junction apacitance capacitances in the PN. hannel apacitance Source Gate rain PMOS I high-to-low transition: p Keqp nj p + Keqswp Ppjswp F j rea um Sidewall 3um G can be: G Gate cap. to bulk G Gate cap. to drain GS Gate cap. to source GS G W G GN ependent on oxide capacitance and area OX (F/μm ) W (μm ) hannel apacitance Gate-hannel apacitance ut o inear (Table 3-4) To ulk To Source To rain Total Gate ap. n + n + n + n + G GS G G uto OX W OX W + W Resistive (/) OX W (/) OX W OX W + W Saturation (/3) OX W (/3) OX W + W Saturation G ut o: No channel G G n + n + GS G Resistive: hannel ivide G in two parts Saturation: /3 o hannel to source 6
7 Total Gate ap. Gn capacitances in the PN. Total Gate ap. Gp capacitances in the PN. Gn GS + G + G W + OX W F Gn + + W + W Gp GS G G OX F. um Gp High-to-low transition > Gn is in Saturation and is closing GN. um High-to-low transition > Gp is in uto and is opening GN apacitance capacitances in the PN. capacitances in the PN Total ap in node G n p Gn Gp F GN + G / GS 3 W + eqn n jn n + K + + K P eqswn n jswn F GN 7
8 3 capacitances in the PN. harge Sharing + 3 G / GS W + eqn n jn n + K + + K P eqswn n jswn F 3 GN rea.7um Sidewall.4um 5, calculate the output voltage in the evaluation phase. ssume worst case charge sharing between the precharged node and the internal nodes in the PN out Qtot out tot Q + + tot tot out + + << out + -> NN harge Sharing Worst case when -transistor o and when the and 3 nodes are uncharged harge Sharing 5, calculate the output voltage in the evaluation phase. ssume worst case charge sharing between the precharged node and the internal nodes in the PN F 3.8 F (+).4 F , suggest a solution to the charge sharing problem (+) Weak (+) 63 % o 8
9 Propagation elay ong hannel Model Propagation elay ong hannel Modell 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor ( OH - O ) Q Δ U kp k p Q I t ( - ) t ( - ) t t ph GS Tp ph Tp ph k k p( - Tp) p Ideal step on clock (+) 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor Precharged to 3 (+) t ph kp( ) ' W kp ( ) ps ( 3).38 t ph ' W kp ( Tp) ( 3) 5ps ( 3 (.6)).38 Propagation delay (page ) Short hannel Transistor 3 t ph.69 4 I ST.5 ' W STp kp STp ( Tp ) ( 3).5 33 ps (.3) ( 3 (.6) ).38 Equivalent Resistance I (m) I I / S R ( OUT ) + R ( OUT /) Req S S I + I Req () ( OUT ) ( OUT /) 9
10 Resistance in The PMOS Transistor Resistance in the PMOS Transistor ong or Short hannel? S () -. I -.84 m I - 6m S () R.84.6 eq p 3. kω -. GS 3 I ST -.3 ong hannel I (m) GS 3 I (m) ong hannel Resistance in The PMOS Transistor I.66 m I 56m.56 GS 3 S () - - I (m) R eq p 3.6 kω Short hannel Equivalent Resistance (Equation 3.43) R 3 5 λ eq p 4 6 ' W STp kp ( Tp ) STp (.5) ( 3) 4 6. (.3) 6 6 ( 3 (.6)) (.3) k Ω Short hannel
11 Propagation elay Propagation elay 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor t.69 R ph eq p ps t ph 6 ps tph.69 Req -p ps k p (+) t ph 5ps ' W Simulation: kp ( - Tp) 7 ps tph Power elay Product & Power onsump. 8, alculate the power delay product or the irst stage. etermine the power consumption i the operating requency is 5 MHz. Threshold point M 9, determine the threshold point M or the inverter stage ong hannel Power elay Product: Energy consumed per switching event PP 34 J Power onsumption P μw W ' p k. p k ( 6) p p r k ' Wn. n kn M n r ( + Tp ) + Tn.586 (3 + (.6)) r +.586
12 Threshold point M Short hannel Threshold point M Short hannel 9, determine the threshold point M or the inverter stage 9, determine the threshold point M or the inverter stage oth elocity saturated STn STp kn (( M Tn ) STn ) kp(( M + Tp ) STp + ) Solving yields M M STp STn Tn + + r + Tp + kp where r + r k n STp STn kpstp 6 (.3) r.543 k 75.8 n STn STn STp Tn + + r + Tp + M + r (.6)
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