Chapter 3-7. An Exercise. Problem 1. Digital IC-Design. Problem. Problem. 1, draw the static transistor schematic for the function Q = (A+BC)D

Size: px
Start display at page:

Download "Chapter 3-7. An Exercise. Problem 1. Digital IC-Design. Problem. Problem. 1, draw the static transistor schematic for the function Q = (A+BC)D"

Transcription

1 igital I-esign Problem Parameters rom a.35 um process hapter 3-7 n Exercise, draw the static transistor schematic or the unction (+), ind the corresponding domino gate using a PN net 3, ind the Euler path or the PN and draw the layout capacitances or the PN. ssume that the circuit is precharged to 3. Neglect the wire capacitances 5, determine the output voltage in the evaluation phase. ssume worst case charge sharing between the precharged node and the internal nodes in the PN Problem Parameters rom a.35 um process Problem 6, suggest a solution to the charge sharing problem 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor 8, determine the power-delay product or the irst stage. etermine the power consumption i the operating requency is 5 MHz 9, determine the threshold point M or the inverter stage, draw the static transistor schematic or the unction Q (+) The unction is non-inverting, i.e. a two stage operation. Make the inverse unction o Q ollowed by an inverter. The PN or the irst stage is Q ( + ). and are placed in series and both are in parallel with. is placed in series with the other. The PUN is ound by e Morgan law s or by duality i.e. serial connections in PN corresponds to parallel in the PUN and vice versa.

2 Static Gate omino ogic, draw the static transistor schematic or the unction Q (+), ind the corresponding domino gate using a PN net (+) PN omino ogic Euler Path, ind the corresponding domino gate using a PN net 3, ind the Euler path or the PN and draw the layout (+) (+) (+) Static gate

3 Euler Path and ayout Parasitic apacitances 3, ind the Euler path or the PN and draw the layout capacitances in the PN. ssume that the circuit is precharged to 3. Neglect the wire capacitances. (+) Euler Path 3 (+) 3 Note: the path goes through the ground GN GN apacitance capacitances in the PN. Overlap apacitance Gate consists o: Source rain Overlap in the,, and Φ p-transistor iusion in n- and p- drain areas G o W GS o W GS W G hannel & Overlap in the inverter Wire is neglected GN G is a constant per unit length in F/um 3

4 The Miller Eect Parameters.35um Δ I gd is modeled rom out to GN, the value shall be doubled gd Δ Δ gd W Δ gd Electrical Parameters apacitances k n 75 m/ ox 4.6 F/mm Tn.5 ( gd gs ). F/mm (.35mm).3 mm jn.93 F/mm W (.6mm).55 mm jp.4 F/mm γ n.58 / jswn.8 F/mm λ n.5 / k p -6 m/ jswp.38 F/mm Tp (.35mm).38 mm W (.6mm).55 mm γ p -.5 / λ p -.5 / elocity Saturation STn.8 STp -.3 Overlap ap. gd capacitances in the PN. Junction apacitance GN -> / or -> / transition is assumed (to 5% point) rain/source iusion ottom i ot + SW 3 ( W) gd F 6(.. μm) μm 6.6 F G Gate Towards hannel W on t count the wall towards the channel GN s Side Wall 4

5 Junction apacitance capacitances in the PN. etermine K eq : Example K + K P n eqn n j eqswn n jsw High-to-low transition ( to /) NMOS, ottom plate etermine K eq (see eq 5.4) p m.5;.9 ; 3 ;.5 High ow K eq (( ) ( ) High ow ) ( )( m) m m m High ow Transition to 5% point Note: Reverse biased voltages (diodes) i.e. negative voltages n GN K eq (( High) ( ow) ) m m m ( )( m ) High ow ( ) (.9 + 3) (.9 +.5) ( 3+.5)(.5).54 etermine K eq Junction apacitance capacitances in the PN. NMOS,.35 um technology, 3 High-to-low ottom plate K eqn.54 High-to-low Sidewall K eqswn.58 ow-to-high ottom plate K eqn.76 ow-to-high Sidewall K eqswn.78 NMOS I high-to-low transition: n Keqn nj n + Keqswn Pnjswn F j PMOS,.35 um technology, 3 High-to-low ottom plate K eqp.77 High-to-low Sidewall K eqswp.84 rea um Sidewall um ow-to-high ottom plate K eqp.55 ow-to-high Sidewall K eqswp.67 GN 5

6 Junction apacitance capacitances in the PN. hannel apacitance Source Gate rain PMOS I high-to-low transition: p Keqp nj p + Keqswp Ppjswp F j rea um Sidewall 3um G can be: G Gate cap. to bulk G Gate cap. to drain GS Gate cap. to source GS G W G GN ependent on oxide capacitance and area OX (F/μm ) W (μm ) hannel apacitance Gate-hannel apacitance ut o inear (Table 3-4) To ulk To Source To rain Total Gate ap. n + n + n + n + G GS G G uto OX W OX W + W Resistive (/) OX W (/) OX W OX W + W Saturation (/3) OX W (/3) OX W + W Saturation G ut o: No channel G G n + n + GS G Resistive: hannel ivide G in two parts Saturation: /3 o hannel to source 6

7 Total Gate ap. Gn capacitances in the PN. Total Gate ap. Gp capacitances in the PN. Gn GS + G + G W + OX W F Gn + + W + W Gp GS G G OX F. um Gp High-to-low transition > Gn is in Saturation and is closing GN. um High-to-low transition > Gp is in uto and is opening GN apacitance capacitances in the PN. capacitances in the PN Total ap in node G n p Gn Gp F GN + G / GS 3 W + eqn n jn n + K + + K P eqswn n jswn F GN 7

8 3 capacitances in the PN. harge Sharing + 3 G / GS W + eqn n jn n + K + + K P eqswn n jswn F 3 GN rea.7um Sidewall.4um 5, calculate the output voltage in the evaluation phase. ssume worst case charge sharing between the precharged node and the internal nodes in the PN out Qtot out tot Q + + tot tot out + + << out + -> NN harge Sharing Worst case when -transistor o and when the and 3 nodes are uncharged harge Sharing 5, calculate the output voltage in the evaluation phase. ssume worst case charge sharing between the precharged node and the internal nodes in the PN F 3.8 F (+).4 F , suggest a solution to the charge sharing problem (+) Weak (+) 63 % o 8

9 Propagation elay ong hannel Model Propagation elay ong hannel Modell 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor ( OH - O ) Q Δ U kp k p Q I t ( - ) t ( - ) t t ph GS Tp ph Tp ph k k p( - Tp) p Ideal step on clock (+) 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor Precharged to 3 (+) t ph kp( ) ' W kp ( ) ps ( 3).38 t ph ' W kp ( Tp) ( 3) 5ps ( 3 (.6)).38 Propagation delay (page ) Short hannel Transistor 3 t ph.69 4 I ST.5 ' W STp kp STp ( Tp ) ( 3).5 33 ps (.3) ( 3 (.6) ).38 Equivalent Resistance I (m) I I / S R ( OUT ) + R ( OUT /) Req S S I + I Req () ( OUT ) ( OUT /) 9

10 Resistance in The PMOS Transistor Resistance in the PMOS Transistor ong or Short hannel? S () -. I -.84 m I - 6m S () R.84.6 eq p 3. kω -. GS 3 I ST -.3 ong hannel I (m) GS 3 I (m) ong hannel Resistance in The PMOS Transistor I.66 m I 56m.56 GS 3 S () - - I (m) R eq p 3.6 kω Short hannel Equivalent Resistance (Equation 3.43) R 3 5 λ eq p 4 6 ' W STp kp ( Tp ) STp (.5) ( 3) 4 6. (.3) 6 6 ( 3 (.6)) (.3) k Ω Short hannel

11 Propagation elay Propagation elay 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor 7, calculate the t ph in the precharged node when all input signals are low during precharge. Use the physical model irst and compare the result with the equivalent resistor model or the transistor t.69 R ph eq p ps t ph 6 ps tph.69 Req -p ps k p (+) t ph 5ps ' W Simulation: kp ( - Tp) 7 ps tph Power elay Product & Power onsump. 8, alculate the power delay product or the irst stage. etermine the power consumption i the operating requency is 5 MHz. Threshold point M 9, determine the threshold point M or the inverter stage ong hannel Power elay Product: Energy consumed per switching event PP 34 J Power onsumption P μw W ' p k. p k ( 6) p p r k ' Wn. n kn M n r ( + Tp ) + Tn.586 (3 + (.6)) r +.586

12 Threshold point M Short hannel Threshold point M Short hannel 9, determine the threshold point M or the inverter stage 9, determine the threshold point M or the inverter stage oth elocity saturated STn STp kn (( M Tn ) STn ) kp(( M + Tp ) STp + ) Solving yields M M STp STn Tn + + r + Tp + kp where r + r k n STp STn kpstp 6 (.3) r.543 k 75.8 n STn STn STp Tn + + r + Tp + M + r (.6)

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational

More information

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

ECE321 Electronics I

ECE321 Electronics I EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1

More information

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

Digital Microelectronic Circuits ( )

Digital Microelectronic Circuits ( ) Digital Microelectronic ircuits (361-1-3021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,

More information

CMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare. ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler

More information

MOS SWITCHING CIRCUITS

MOS SWITCHING CIRCUITS ontent MOS SWIHING IRUIS nmos Inverter nmos Logic Functions MOS Inverter UNBUFFR MOS LOGI BUFFR MOS LOGI A antoni 010igital Switching 1 MOS Inverters V V V V V R Pull Up Pu Pu Pu Pull own G B Pd Pd Pd

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

Lecture 12 CMOS Delay & Transient Response

Lecture 12 CMOS Delay & Transient Response EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties. CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University

More information

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section Announcements EE0 - Fall 00 Microelectronic evices and Circuits ecture 7 Homework, due today Homework due net week ab this week Reading: Chapter MO Transistor ecture Material ast lecture iode currents

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

EE115C Digital Electronic Circuits Homework #4

EE115C Digital Electronic Circuits Homework #4 EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

More information

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

B.Supmonchai August 1st, q In-depth discussion of CMOS logic families. q Optimizing gate metrics. q High Performance circuit-design techniques

B.Supmonchai August 1st, q In-depth discussion of CMOS logic families. q Optimizing gate metrics. q High Performance circuit-design techniques ugust st, 4 Goals of This hapter hapter 6 Static MOS ircuits oonchuay Supmonchai Integrated esign pplication Research (IR) Laboratory ugust, 4; Revised - June 8, 5 In-depth discussion of MOS logic families

More information

Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter

Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)

More information

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power - Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

! Inverter Power. ! Dynamic Characteristics. " Delay ! P = I V. ! Tricky part: " Understanding I. " (pairing with correct V) ! Dynamic current flow:

! Inverter Power. ! Dynamic Characteristics.  Delay ! P = I V. ! Tricky part:  Understanding I.  (pairing with correct V) ! Dynamic current flow: ESE 570: Digital Integrated ircuits and LSI Fundamentals Lecture Outline! Inverter Power! Dynamic haracteristics Lec 10: February 15, 2018 MOS Inverter: Dynamic haracteristics " Delay 3 Power Inverter

More information

COMBINATIONAL LOGIC. Combinational Logic

COMBINATIONAL LOGIC. Combinational Logic COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

More information

Lecture 4: CMOS review & Dynamic Logic

Lecture 4: CMOS review & Dynamic Logic Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br

More information

Delay and Power Estimation

Delay and Power Estimation EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What

More information

EECS 312: Digital Integrated Circuits Midterm Exam Solutions 12 March 2009

EECS 312: Digital Integrated Circuits Midterm Exam Solutions 12 March 2009 Signature: EECS 312: igital Integrated Circuits Midterm Exam Solutions 12 March 2009 Robert ick Show your work. erivations are required for credit; end results are insufficient. Closed book. No electronic

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe57-3f

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

! MOS Capacitances.  Extrinsic.  Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

More information

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 Review Voltage wing of PT Driving an Inverter PE/EE 47, PE 57 VLI Design I L9: MO & Wire apacitances Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation. Where Does Power Go in CMOS? Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

More information

Motivation for Lecture. For digital design we use CMOS transistors. Gate Source. CMOS symboler. MOS transistor. Depletion. A channel is created

Motivation for Lecture. For digital design we use CMOS transistors. Gate Source. CMOS symboler. MOS transistor. Depletion. A channel is created Motivation for Lecture igital Integrated ircuits iktor Öwall o see how standard gates are implemented with transistors? How does technology affect the performance, e.g. speed and power consumption? What

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design

THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design chapter5.fm Page 176 Friday, January 18, 2002 9:01 M CHPTER 5 THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Introduction

More information

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

Lecture 4: DC & Transient Response

Lecture 4: DC & Transient Response Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

More information

EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1

EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1 RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero

More information

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

Lecture 23. CMOS Logic Gates and Digital VLSI I

Lecture 23. CMOS Logic Gates and Digital VLSI I ecture 3 CMOS ogic Gates and Digital SI I In this lecture you will learn: Digital ogic The CMOS Inverter Charge and Discharge Dynamics Power Dissipation Digital evels and Noise NFET Inverter Cut-off Saturation

More information

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power

More information

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain rain G Gate

More information

Practice 7: CMOS Capacitance

Practice 7: CMOS Capacitance Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999 UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

5. CMOS Gate Characteristics CS755

5. CMOS Gate Characteristics CS755 5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor

More information

Errata of K Introduction to VLSI Systems: A Logic, Circuit, and System Perspective

Errata of K Introduction to VLSI Systems: A Logic, Circuit, and System Perspective Errata of K13126 Introduction to VLSI Systems: A Logic, Circuit, and System Perspective Chapter 1. Page 8, Table 1-1) The 0.35-µm process parameters are from MOSIS, both 0.25-µm and 0.18-µm process parameters

More information

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files - Design Rules

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files - Design Rules EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files - esign Rules Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate

More information

Dynamic operation 20

Dynamic operation 20 Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ECE321 Electronics I

ECE321 Electronics I ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS

More information

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

CMOS Logic Gates. University of Connecticut 172

CMOS Logic Gates. University of Connecticut 172 CMOS Logic Gates University of Connecticut 172 Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

More information

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16] Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an n-channel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3

More information

COMP 103. Lecture 16. Dynamic Logic

COMP 103. Lecture 16. Dynamic Logic COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03

More information

Digital Integrated Circuits 2nd Inverter

Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response

More information

! Energy Optimization. ! Design Space Exploration. " Example. ! P tot P static + P dyn + P sc. ! Steady-State: V in =V dd. " PMOS: subthreshold

! Energy Optimization. ! Design Space Exploration.  Example. ! P tot P static + P dyn + P sc. ! Steady-State: V in =V dd.  PMOS: subthreshold ESE 570: igital Integrated ircuits and VLSI undamentals Lec 17: March 26, 2019 Energy Optimization & esign Space Exploration Lecture Outline! Energy Optimization! esign Space Exploration " Example 3 Energy

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information