B.Supmonchai August 1st, q In-depth discussion of CMOS logic families. q Optimizing gate metrics. q High Performance circuit-design techniques

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1 ugust st, 4 Goals of This hapter hapter 6 Static MOS ircuits oonchuay Supmonchai Integrated esign pplication Research (IR) Laboratory ugust, 4; Revised - June 8, 5 In-depth discussion of MOS logic families Static and ynamic Pass-Transistor Nonratioed and Ratioed Logic Optimizing gate metrics rea, Speed, Energy or Robustness High Performance circuit-design techniues -545 igital Is Static MOS ircuits ombinational vs. Seuential Logic Static MOS ircuits In ombinational Logic ircuit ombinational put = f(in) In ombinational Logic ircuit State Seuential put = f(in, Previous In) t every point in time (except during the switching transients) each gate output is connected to either or V SS via a low-resistance path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods) This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is

2 ugust st, 4 Static omplementary MOS Threshold rops Pull-Up Network: make a connection from to when (In,In, In N ) = PUN S In In In N In In In N PUN PN PMOS transistors only (In,In, In N ) NMOS transistors only Pull-own Network: make a connection from to GN when (In,In, In N ) = PN Æ S V GS Æ Æ V Tp V GS S L Æ - V Tn PUN and PN are dual logic networks S -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 6 onstruction of PN onstruction of PUN Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high + PMOS switch closes when switch control input is low. = + + = Series = NOR Parallel = NN Series = NN Parallel = NOR PMOS Transistors pass a strong but a weak NMOS Transistors pass a strong but a weak -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is

3 ugust st, 4 uality of PUN and PN Example: MOS NN gate PUN and PN are dual networks e Morgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] parallel connection of transistors in the PUN corresponds to a series connection of the PN omplementary gate is naturally inverting (NN, NOR, OI, OI) PN: G = PUN: = + onduction to GN onduction to Number of transistors for an N-input logic gate is N G(In, In,, In N ) = (In, In,, In N ) -545 igital Is Static MOS ircuits igital Is Static MOS ircuits Example: MOS NOR gate omplex MOS Gate + OUT = + ( + ) erive PUN hierarchically by identifying sub-nets -545 igital Is Static MOS ircuits -545 igital Is Static MOS ircuits -545 igital Is 3

4 ugust st, 4 ell esign: n Introduction Standard ells general purpose logic Synthesizable Same height but varying width atapath ells or regular, structured designs (arithmetic) Including some wiring in the cell ixed height and width Example of Standard ell N Well Minimum-Size Inverter l ell boundary In GN ell height metal tracks Metal track is approx. 3l + 3l Pitch = repetitive distance between objects ell height is pitch Rails ~l -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 4 Standard ell Layout Methodology 98s Standard ell Layout Methodology 99s Routing channel No Routing channels Mirrored ell signals M GN M3 GN Routing channel What logic function is this? Mirrored ell GN -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 4

5 ugust st, 4 Stick iagrams OI Logic Graph ontains no dimensions Represents relative positions of transistors j Node of the circuit PUN = ( + ) i GN In Inverter GN NN i Transition ontrol j GN PN -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 8 Two Stick iagrams of ( + ) onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists an Euler path in the logic graph i Euler path: a path through all nodes in the graph such that each edge is visited once and only once. GN GN j GN rossover can be eliminated by re-ordering inputs -545 igital Is Static MOS ircuits 9 or a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) -545 igital Is Static MOS ircuits -545 igital Is 5

6 ugust st, 4 OI Logic Graph OI Layout PUN = (+) (+) GN PN GN -545 igital Is Static MOS ircuits Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) -545 igital Is Static MOS ircuits NOR/OR Implementation VT is ata-ependent NOR OR 3.5m/.5m NMOS.75m /.5m PMOS M 3 M 4,: -> = =, : -> =, :-> weaker M PUN V GS = V V S S M int V GS = V S How many transistor in each? an you create the stick diagrams for the lower left circuit? -545 igital Is Static MOS ircuits 3 VT haracteristics are dependent upon the data input patterns applied to the gate (so the noise margins are also data dependent!) -545 igital Is Static MOS ircuits igital Is 6

7 ugust st, 4 Observation I Review: MOS Inverter - ynamic The difference between the blue and the orange lines results from the state of internal node int between the two NMOS evices. t phl = f(r n, ) The threshold voltage of M is higher than M due to the body effect (g), V S of M is not zero (when V = ) due to the presence of int R n V out t phl =.69 R en t phl =.69 (3/4 ( )/ I STn ) =.5 / (W/L n k n V STn ) V Tn = V Tn and V Tn = V Tn + g( ( f + V int ) - f ) V in = V propagation delay is determined by the time to charge and discharge the load capacitor -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 6 Review: esigning for Performance Switch elay Model Reduce Increase W/L ratio of the transistor the most powerful and effective performance optimization tool watch out for self-loading! R p R p R e R p Increase only minimal improvement in performance at the cost of increased energy dissipation R n R p R p int Slope engineering - keeping signal rise and fall times smaller than or eual to the gate propagation delays and of approximately eual values R n int R n R n R n good for performance and power consumption NN INVERTER NOR -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 7

8 ugust st, 4 Input Pattern Effects on elay elay ependence on Input Patterns R p R n R n R p int elay is dependent on the pattern of inputs Low to high transition both inputs go low delay is.69 R p / since two p-resistors are on in parallel one input goes low delay is.69 R p High to low transition both inputs go high delay is.69 R n Voltage [V] ==Æ = Æ, = =, =Æ time [ps] Input ata Pattern ==Æ =, =Æ = Æ, = ==Æ =, =Æ = Æ, = elay (psec) NN dding transistors in series (without sizing) slows down the circuit NMOS =.5mm/.5 mm, PMOS =.75mm/.5 mm, = f -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 3 Transistor Sizing asic Inverter as a reference circuit In (W/L) p evice Transconductance (See Supplement ) k n = k n (W/L) n = (µ n e ox /t ox )((W/L) n k p = k p (W/L) p = (µ p e ox /t ox )((W/L) p or rise time eual to fall time, k p = k n (R p = R n ) (W/L) n ecause µ p ~ µ n / (W/L) p = (W/L) n The size of PMOS must be twice as large as that of NMOS -545 igital Is Static MOS ircuits 3 Transistor Sizing: NN and NOR R p R p R PN = R n + R n R n R n NN Symmetric Response R PUN = R PN int R p µ /(W/L) p R n µ /(W/L) n R PUN = R p + R p R n R n -545 igital Is Static MOS ircuits NOR R p R p int -545 igital Is 8

9 ugust st, 4 Note on Transistor Sizing y assuming R PUN = R PN, we ignores the extra diffusion capacitance introduced by widening the transistors. In SM, even larger increases in the width are needed due to velocity saturation. or -input NNs, the NMOS transistors should be made.5 times as wide. NN implementation is clearly preferred over a NOR implementation, since a PMOS stack series is slower than an NMOS stack due to lower carrier mobility -545 igital Is Static MOS ircuits Transistor Sizing: omplex MOS Gate Red sizing assuming R PUN = R PN ollow short path first; note PMOS for and,4 rather than 3 (average in pull-up chain of three = (4+4+)/3) lso note structure of pull-up and pull-down to minimize diffusion cap. at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where R p = 3R n ) Sizing rules of thumb: PMOS = 3 * NMOS -545 igital Is Static MOS ircuits 34 an-in onsiderations 3 istributed R model (Elmore delay) t phl =.69 R en ( ) Propagation delay deteriorates rapidly as a function of fan-in uadratically in the worst case. Notes on an-in onsiderations While output capacitance makes full swing transition from to, internal nodes only swing from -V Tn to GN,, and 3, each includes junction capacitance as well as the gate-to-source and gate-to-drain capacitances (turned into capacitances to ground using the Miller effect) or W/L of.5/.5 NMOS and.375/.5 PMOS, values are on the order of.85 f = 3.47 f with NO output load (all of diffusion capacitance = intrinsic capacitance of the gate itself). t phl = 85 ps (simulated as 86 ps). The simulated worst case low-to-high delay was 6 ps igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 9

10 ugust st, 4 t p as a unction of an-in t p (psec) 5 uadratic 75 5 t phl t p 5 t plh linear fan-in Gates with a fan-in greater than 4 should be avoided igital Is Static MOS ircuits 37 t p as a unction of an- t p (psec) ll gates have the same drive current. t p NOR 8 6 t p INV eff. fan-out t p NN Slope is a function of driving strength -545 igital Is Static MOS ircuits 38 t p as a unction of an-in and an- an-in: uadratic due to increasing resistance and capacitance an-out: each additional fan-out gate adds two gate capacitances to Parallel hain t p = a I + a I + a 3 O Serial hain -545 igital Is Static MOS ircuits 39 ast omplex Gates: esign Techniue Transistor sizing as long as fan-out capacitance dominates Progressive sizing In N In 3 In In MN M3 M M 3 istributed R line M > M > M3 > > MN (the ET closest to the output should be the smallest) an reduce delay by more than %; decreasing gains as technology shrinks -545 igital Is Static MOS ircuits igital Is

11 ugust st, 4 Notes on esign Techniue With transistor sizing, if the load capacitance is dominated by the intrinsic capacitance of the gate, widening the device only creates a self loading effect and the propagation delay is unaffected (and may even become worse). or progressive sizing, M have to carry the discharge current from M ( ), M3 ( ), MN and so make it the largest. MN only has to discharge the current from MN ( )(no internal capacitances). While progressive sizing is easy in a schematic, in a real layout it may not pay off due to design-rule considerations that force the designer to push the transistors apart increasing internal capacitance igital Is Static MOS ircuits 4 charged charged delay determined by time to discharge, and ast omplex Gates: esign Techniue Input re-ordering when not all inputs arrive at the same time In 3 In In Æ critical path M3 M M charged L Æ In In In 3 critical path charged discharged discharged delay determined by time to discharge Place latest arriving signal (critical path) closest to the output can result in a speed up igital Is Static MOS ircuits 4 M3 M M Example: Sizing and Ordering Effects = f Progressive sizing in pull-down chain gives up to a 3% improvement. Input ordering saves 5% critical path 3% critical path 7% -545 igital Is Static MOS ircuits 43 ast omplex Gates: esign Techniue 3 lternative logic structures Reduced fan-in results in deeper logic depth = EGH Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate igital Is Static MOS ircuits igital Is

12 ugust st, 4 Notes on esign Techniue 3 Reducing fan-in increases logic depth of the circuit More stages but each stage has smaller delay Only simulation will tell which of the two alternative configurations is faster and has lower power dissipation. ast omplex Gates: esign Techniue 4 Isolating fan-in from fan-out using buffer insertion Optimizing the propagation delay of a gate in isolation is misguided. Reduce on large fan-in gates, especially for large, and size the inverters progressively to handle the more effectively -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 46 ast omplex Gates: esign Techniue 5 Reducing the voltage swing t phl =.69 (3/4 ( )/ I STn ) =.69 (3/4 ( V swing )/ I STn ) linear reduction in delay also reduces power consumption ut the following gate is much slower! Or reuires the use of sense amplifiers on the receiving end to restore the signal level (memory design) -545 igital Is Static MOS ircuits 47 Sizing Logic Paths for Speed reuently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: LU load in an Intel s microprocessor is.5p How do we size the LU data path to achieve maximum speed? We have already solved this for the inverter chain can we generalize it for any type of logic? -545 igital Is Static MOS ircuits igital Is

13 ugust st, 4 Inverter hain: Recap elay of a omplex Logic Gate In f f N- N or a complex gate, we expand the inverter chain euation Ê t p = t p + ˆ ext Á Ë g g = t Ê + f ˆ p Á Ë g Ê t p = t p Á p + g f Ë g ˆ N or given N: i+ / i = i / i- = f = ( / in ) or optimum performance, we try to keep f ~ 4, which give us the number of stages, N. an the same approach (logical effort) be used for any combinational circuit? -545 igital Is Static MOS ircuits 49 t p is the intrinsic delay of an inverter f is the effective fan-out ( ext / g ) - also called the electrical effort p is the ratio of the intrinsic (unloaded) delay of the complex gate and a simple inverter (a function of the gate topology and layout style) g is the logical effort -545 igital Is Static MOS ircuits 5 Notes on elay of a Logic Gate Logical effort first defined by Sutherland and Sproull in 999. In a simpler format, Gate delay: Effort delay: Effort delay Logical Effort = h + p h = g f Intrinsic delay Electrical = Effort out / in (effective fan-out) -545 igital Is Static MOS ircuits 5 Intrinsic elay Term, p The more involved the structure of the complex gate, the higher the intrinsic delay compared to an inverter Gate Type Inverter n-input NN n-input NOR n-way mux OR, NOR n n- Ignoring second order effects such as internal node capacitances -545 igital Is Static MOS ircuits 5 p n n n -545 igital Is 3

14 ugust st, 4 Logical Effort Term, g Logical effort of a gate, g, presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current g represents the fact that, for a given load, complex gates have to work harder than an inverter to produce a similar (speed) response Gate Type Inverter NN NOR Mux OR g (for to 4 input gates) 4/3 5/ /3 7/3 4 (n+)/3 (n+)/3 Notes on Logical Effort Inverter has the smallest logical effort and intrinsic delay of all static MOS gates Logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver same output current) Logical effort is a function of topology, independent of sizing Logical effort increases with the gate complexity Electrical effort (Effective fanout) is a function of load/gate size -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 54 Example of Logical Effort ssuming a PMOS/NMOS ratio of, the input capacitance of a minimum-sized inverter is three times the gate capacitance of a minimum-sized NMOS ( unit ) unit = 3 unit = igital Is Static MOS ircuits unit = 5 elay as a unction of an- normalized delay NN: g=4/3, p = fan-out f INV: g=, p= effort delay intrinsic delay Gate Effort: h = fg -545 igital Is Static MOS ircuits 56 The slope of the line is the logical effort of the gate The y-axis intercept is the intrinsic delay an adjust the delay by adjusting the effective fan-out (by sizing) or by choosing a gate with a different logical effort -545 igital Is 4

15 ugust st, 4 Path elay: omplex Logic Gate Network Total path delay through a combinational logic block t p = Â t p,j = t p Â(p j + (f j g j )/g ) So, the minimum delay through the path determines that each stage should bear the same gate effort Path elay Euation erivation The path logical effort, G = g i nd the path effective fan-out (path electrical effort) is = /g The branching effort accounts for fan-out to other gates in the network f g = f g =... = f N g N b = ( on-path + off-path )/ on-path onsider optimizing the delay through the logic network a b c 5 how do we determine a, b, and c sizes? The path branching effort is then = b i The total path effort is then H = G So, the minimum delay through the path is N = t p ( Âp j + (N H)/ g) -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 58 Example: omplex Logic Gates or gate i in the chain, its size is determined by or this network = / g = 5 G = x 5/3 x 5/3 x = 5/9 = (no branching) 4 H = G = 5/9, so the optimal stage effort is H =.93 ÿ an-out factors are f =.93, f =.93 x 3/5 =.6, f 3 =.6, f 4 =.93 So the gate sizes are a = f g /g =.6, b = f f g /g 3 =.34 and c = f f f 3 g /g 4 =.6 i - s i = (g s )/g i (f j /b j ) j= a b c 5 Example 8-input N -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 5

16 ugust st, 4 Summary: Method of Logical Effort ompute the path effort: = GH ind the best number of stages N ~ log 4 ompute the stage effort f = /N Sketch the path with this number of stages Work either from either end, find sizes: in = out *g/f Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 999. Summary: Key efinitions Sutherland, Sproull Harris -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 6 Ratioed Logic Ratioed Logic: ctive Loads Goal: To Reduce the number of devices over complementary MOS In In In 3 Resistive Load PN R L N transistors + Load V OH = V OL = R PN / (R PN + R L ) symmetrical Response Static Power consumption P low epletion Load In In In 3 V T < PN V SS PMOS Load In In In 3 V SS PN V SS V SS t pl =.69 R L depletion load NMOS pseudo-nmos -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 6

17 ugust st, 4 Pseudo NMOS NN and NOR NN -545 igital Is Static MOS ircuits 65 NOR Psedo-NMOS is useful when area is most important Reduce transistor counts Used occasionally for large fan-in gates k n Pseudo-NMOS Inverter haracteristics ssumptions: NMOS resides in linear mode V OL is small relative to the gate drive ( -V T )) Ê ( -V Tn )V OL - V ˆ Ê OL Á + k p (- -V Tp ) V STp - V ˆ STp Á = Ë Ë V OL = k p( + V Tp ) V STp k n ( -V Tn ) ª m nw p m p W n V STp Ê P low = I low ª k p (- -V Tp ) V STp - V ˆ STp Á Ë -545 igital Is Static MOS ircuits 66 Pseudo-NMOS Inverter VT V out (V) W/L p =.5 W/L p =.5 W/L p = W/L p = 4 W/L p = NMOS size =.5 µm/.5 µm Size V in (V) igital Is Static MOS ircuits P stat (µw) Larger pull-up device not only improves performance (delay) but also increases power dissipation and lowers noise margins by increasing V OL V OL (V) t plh (ps) Improved Loads: daptive Load Enable nable M M M -545 igital Is Static MOS ircuits 68 M >> M The idea is to reduce static power consumption by adjusting the load Load M when there are not too many inputs (,,, or ) active Switch to Load M when all inputs are active (thus reuire high amount of current to drive) -545 igital Is 7

18 ugust st, 4 Improved Loads: VSL VSL Example M M PN PN V SS V SS ifferential ascode Voltage Switch Logic (VSL) OR-NOR gate -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 7 VSL haracteristics VSL Transient Response ual Rail Logic Each input is provided in complementary format and each gate produces complementary output Increasing complexity Rail-to-Rail Swing No static power dissipation Sizing of the PMOS relative to PN is critical to functionality, not just performance PNs must be strong enough to bring outputs below - V Tp Voltage [V].5.5.5,, Time [ns] t in->out = 97 ps t in->out = 3 ps Transient Response of a -input N/NN gate. How does it look like? -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 8

19 ugust st, 4 NMOS Transistors in Series/Parallel PMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals Primary inputs drive both gate and source/drain terminals NMOS switch closes when the gate input is high PMOS switch closes when the gate input is low Y = Y if and Y = Y if and = + Y = Y if or Y = Y if or = Remember - NMOS transistors pass a strong but a weak Remember - PMOS transistors pass a strong but a weak -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 74 VT of PT N Gate omplementary PT Logic (PL).5/.5.5/.5.5/.5.5/.5 V out, (V) = =, = Æ =, = Æ = = Æ V in, (V) l Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static MOS inverter insertion) N/NN = = PT Network Inverse PT Network OR/NOR =+ =+ OR/NOR = = -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 9

20 ugust st, 4 PL Properties ifferential, so complementary data inputs and outputs are always available (don t need extra inverters) Static, since the output defining nodes are always tied to or GN through a low resistance path esign is modular; all gates use the same topology, only the inputs are permuted. Simple OR makes it attractive for structures like adders ast! (assuming number of transistors in series is small) dditional routing overhead for complementary signals Still have static power dissipation problems -545 igital Is Static MOS ircuits 78 NMOS-Only PT riving an Inverter = In = V GS S V x does not pull up to, but V Tn Threshold voltage drop causes static power consumption (M may be weakly conducting forming a path from to GN) Notice V Tn increases of pass transistor due to body effect (V S ) -545 igital Is Static MOS ircuits 79 V x M M Voltage Swing of PT riving an Inverter In = Æ S.5/.5.5/.5.5/.5 Voltage (V) 3 In =.8V ascaded NMOS-Only PTs = G = M = S x = - V Tn = G y M S = M x = y M ody effect large V S at - when pulling high ( is tied to GN and S charged up close to ) So the voltage drop is even worse V x = - (V Tn + g( ( f f + V x ) - f f )) -545 igital Is Static MOS ircuits Time (ns) Swing on y = - V Tn - V Tn Swing on y = - V Tn Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins -545 igital Is Static MOS ircuits igital Is

21 ugust st, 4 Solution : Level Restorer Transient Level Restorer ircuit Response M r M n x Level Restorer M M ull swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high Voltage (V) 3 W/L n =.5/.5, W/L =.5/.5, W/L =.5/.5 W/L r =./ Time (ps) W/L r =.75/.5 W/L r =.5/.5 node x never goes below V M of inverter so output never switches W/L r =.5/.5 Æ Æ M r O ON or correct operation M r must be sized correctly (ratioed) Restorer has speed and power impacts: Increases the capacitance at x, slowing down the gate Increases t r (but decreases t f ) -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 83 Notes on Level Restorer Pull down must be stronger than restorer (pull up) to switch node If resistance of restorer transistor is too small (too wide transistor) it is impossible to bring the voltage at node below the switching threshold of the inverter, and the inverter never switches! Sizing of M r is critical for functionality, not just performance!! It belongs to ynamic Logic amily -545 igital Is Static MOS ircuits 84 Solution : Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to ) In = V In =.5V =.5V on low V T transistors -545 igital Is Static MOS ircuits 85 off but leaking = V sneak path Watch out for subthreshold current flowing through PTs -545 igital Is

22 ugust st, 4 Solution 3: Transmission Gates (TGs) Most widely used solution = = GN = GN = GN Resistance of TG Resistance (kw) R p R n R e V out (V) R e = R p R n W/L p =.5/.5 V R p.5v V out R n.5v W/L n =.5/.5 = = ull swing bidirectional switch controlled by the gate signal, = if = -545 igital Is Static MOS ircuits 86 TG is not an ideal switch - series resistance R e is relatively constant ( about 8kohms in this case), so can assume has a constant resistance -545 igital Is Static MOS ircuits 87 TG Multiplexer Transmission Gate OR S S S In off S off In 6 Transistors S =!(In S + In S) GN In S S In always has a connection to or GN - not dynamic No voltage drop -545 igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is

23 ugust st, 4 Transmission Gate OR Transmission Gate OR () () off on when = weak = = off on weak when = ( ) ( ) When =, the circuit behaves as if it is an inverter, hence ( = ) = When =, the circuit acts as a transmission gate, hence ( = ) = (TG ensures no voltage drop) -545 igital Is Static MOS ircuits igital Is Static MOS ircuits 9 Transmission Gate OR TG ull dder in + Sum ombine the results using Shannon s expansion theorem, = ( = ) + ( = ) = + = -545 igital Is Static MOS ircuits 9 6 Transistors, no more than PTs in series ull swing Similar delay for Sum and arry out -545 igital Is Static MOS ircuits igital Is 3

24 ugust st, 4 elay of a TG hain Notes on TG hain elay V in V in V V i V i R e V R e V i R e V i+ R e V N elay of the R chain (N TG s in series) is t p (V n ) =.69 ÂkR e =.69 R e (N(N+))/ ª.35 R e N -545 igital Is Static MOS ircuits 95 V N elay grows uadratically in N (in this case in the number of TGs in series) and increases rapidly with the number of switches in the chain. E.g., for 6 cascaded minimum-sized TG s, each with an R e of 8kohms. The node capacitance is the sum of the capacitances of two NMOS and PMOS devices (junctions and drains). apacitance values is approx. 3.6 f for low to high transitions. The delay through the chain is t p =.69 R e (N(N+))/ =.69 x 3.6f x 8kΩ x (6x7)/ =.7ns -545 igital Is Static MOS ircuits 96 TG elay Optimization Notes on elay Optimization V in an speed it up by inserting buffers every M switches 5 5 M 5 5 elay of buffered chain (M TG s between buffer) t p =.69 ÎN/M R e (M(M+))/ + (N/M - ) t pbuf M opt =.7 (t pbuf /R e ) ª 3 or V N uffered chain is now linear in N Quadratic in M but M should be small This buffer insertion techniue works to speed up the delay down long wires as well. onsider 6TG chain example. uffers = inverters (making sure correct polarity is output). or.5micron/.5micron NMOSs and PMOSs in the TGs, simulated delay with TG per buffer is 54 ps, for 3TGs is 54ps, and for 4TG is 64ps. The insertion of buffering inverters reduces the delay by a factor of almost igital Is Static MOS ircuits igital Is Static MOS ircuits igital Is 4