! Energy Optimization. ! Design Space Exploration. " Example. ! P tot P static + P dyn + P sc. ! Steady-State: V in =V dd. " PMOS: subthreshold

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1 ESE 570: igital Integrated ircuits and VLSI undamentals Lec 17: March 26, 2019 Energy Optimization & esign Space Exploration Lecture Outline! Energy Optimization! esign Space Exploration " Example 3 Energy and Power asics Total Power! P tot P static + P dyn + P sc Review 5 Operating Modes Static Leakage Power! Steady-State: V in =V dd " PMOS: subthreshold " NMOS: resistive $ I Sp = I S # W ' & e & % % L ( $ V GS V T nkt / q ' $ $ V S '' & ( 1 e % kt / q ( & 1 λv S % ( (! W $ ( I Sn = µ n OX # & ( V GS V T V S V 2 + S * - " L % 2, 6 7 1

2 Static Power Ratioed Logic Total Static Power! I static?! Input low-output high? " I leak! Input high-output low?! P statit p(v out =lowv 2 /R p,on +p(v out =highvi s(w/le -Vt/(nkT/q p(v out =low probability the output is low p(v out =high probability the output is high " I pmos_on " ~V dd /R p,on p(v out =high=1-p(v out =low 8 9 Switching urrents Switching! I switch (t = I sc (t + I dyn (t ynamic Power I sw I dyn I sc Switching Energy Switching Power! o we know what this is? Q =! What is Q? E = P(tdt = I(tV dd dt = V dd I(tdt I dyn (tdt Q = V = E = V dd 2 I(tdt apacitor charging energy I dyn! Every time output switches 0#1 pay: " E = V 2! P dyn = (# 0#1 trans V 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans ½V 2 / time

3 Short ircuit Power Switching! etween V TN and V dd - V TP " oth N and P devices conducting Short ircuit Power Peak urrent Short ircuit Energy! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall % I S ν sat OX W V GS V T V ( ST ' * & 2 I(tdt I t % ' 1( peak sc 2 * & # E = V dd I peak t sc % 1& ( Vin $ 2' Vdd Vdd-Vthp Vthn! Make it look like a capacitance, S " Q=I t " Q=V " " E = V dd I peak t sc 1 %% $ $ '' # # 2 && E = V dd Q S E = V dd ( S V dd = S V 2 dd time Vdd Isc Vout tsc tsc time Short ircuit Energy! Every time switch " lso dissipate short-circuit energy: E = V 2 " ifferent = sc " cs fake capacitance (for accounting Short ircuit Energy! When transistors switch, both nmos and pmos networks may be nano-tarily ON at once! Leads to a blip of short circuit current! < 10% of dynamic power if rise/fall times are comparable for input and output! We will generally ignore this component in hand analysis, but simulated measured results include it

4 Switching Waveforms Switching Power! Every time output switches 0#1 pay: " E = V 2! P dyn = (# 0#1 trans V 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans ½V 2 / time harging Power harging Power! P dyn = (# trans ½V 2 / time! P dyn = (# 0#1 trans V 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle! Often like to think about switching frequency! Useful to consider per clock cycle " requency f = 1/clock-period! P dyn = (#trans/clock ½V 2 f " requency f = 1/clock-period! P dyn = (# 0#1 trans/clock V 2 f Switching Power ctivity actor! P dyn = (#0#1 trans/clock V 2 f! Let a = activity factor a = average #tran 0#1 /clock! Let a = activity factor " a = average #tran 0#1 /clock = 0 p(out i+1! P dyn = av 2 f a = N N N 2 = N 0 (2N N 0 N 2 2N

5 ctivity actor! Let a = activity factor " a = average #tran 0#1 /clock = 0p(out i+1 a = N 0 N 1 2 N 2 = N 0(2 N N 0 N 2 2 N Reduce ynamic Power?! P dyn = av 2 f! How do we reduce dynamic power? Reduce ctivity actor Reduce ctivity actor Tree hain Tree hain = 0p(out i+1 = 0p(out i+1 a = N 0 N 1 2 N 2 = N 0(2 N N 0 N 2 2 N a = N 0 N 1 2 N 2 = N 0(2 N N 0 N 2 2 N Reduce ctivity actor Reduce ctivity actor Tree hain Tree hain 15/256 = 0p(out i+1 = 0p(out i+1 7/64 15/256 a = N 0 N 1 2 N 2 = N 0(2 N N 0 N 2 2 N a = N 0 N 1 2 N 2 = N 0(2 N N 0 N 2 2 N

6 Reduce ctivity actor Total Power Summary Tree hain! P tot = P static + P sc + P dyn 15/256 = 0p(out i+1 a = N 0 N 1 2 N 2 = N 0(2 N N 0 N 2 2 N 7/64 15/256! P sw = P dyn + P sc a( load V 2 f! P tot a( load V 2 f + VI s(w/le -Vt/(nkT/q! Let a = activity factor a = average #tran 0#1 /clock Energy and Power Optimization Power Sources Review: P tot = P static + P dyn + P sc Worksheet Problem 1 Worksheet Problem 1 V in I static I dynamic I sc 0V 140mV 400mV 500mV 600mV 860mV 1V V in I static I dynamic I sc 0V 180p 126u 140mV 6n 100u 400mV 36u 18u 500mV 36u 600mV 36u 18u 860mV 6n 100u 1V 180p 126u

7 Reduce V dd (Worksheet #2 Reduce V dd (Worksheet #2! V dd =520mV, V thn = V thp =300mV! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc V in I static I dynamic I sc 0V 0V 180p 39.6u 140mV 140mV 6n 14.4u 260mV 260mV 111n 360mV 360mV 6n 10.8u 500mV 500mV 180p 36u Reduce V dd esign Tradeoffs! What happens as reduce V dd? " Energy? " Static " Switching " elay? 41 Reduce V dd : Reduce V dd :! τ gd =Q/I=(V/I! τ gd =Q/I=(V/I! I d =(µ OX /2(W/L(V gs -V TH 2! τ gd impact?! τ gd 1 V

8 Reduce V dd :! τ gd =Q/I=(V/I! I d =(µ OX /2(W/L(V gs -V TH 2! τ gd impact? Reduce V dd (Worksheet #3! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds τ/(τ@v dd E switch / (E dd Eτ 2 1V! τ gd 1 V 700mV 500mV! Ignoring leakage: 350mV E V 2 260mV Eτ 2 onst Reduce V dd (Worksheet #3 Increase V th (Worksheet #4! V thn = V thp =300mV, V in =V dd, estimate Eτ! What is impact of increasing threshold on V dd I ds τ/(τ@v dd E switch / (E dd Eτ 2 " elay? " Leakage? 1V 126u 1 1 1! V dd =1V, V in =V dd 700mV 72u mV 36u V thn = -V thp I ds τ/(τ@v th =300mV I static (I th =300mV I stat / 350mV 9u mV 260mV 111n k 460mV 600mV Increase V th (Worksheet #4 Idea! What is impact of increasing threshold on! Tradeoff " elay? " Speed " Leakage? " Switching energy! V dd =1V, V in =V dd " Leakage energy! Energy-elay tradeoff: Eτ 2 V thn = -V thp I ds τ/(τ@v th =300mV I static (I th =300mV I stat / 300mV 126u 1 180p 1 460mV 97u p mV 72u f

9 esign Problem esign Space Exploration! unction: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! ssumptions: Match case uncommon " Ie. Most of the time, the inputs won t be matched! eliberately focus on Energy to complement project " but will still talk about delay Penn ESE 370 all Khanna 50 Penn ESE 370 all Khanna 51 Idea: esign Space Explore Problem Solvable! Identify options! Is it feasible? " ll the knobs you can turn! Explore space systematically " irst, make sure we have a solution so we know our main goal is optimization! ormulate continuum where possible " i.e. formulate trends and tradeoffs quantitatively! How do we decompose the problem? Penn ESE 370 all Khanna 52 Penn ESE 370 all Khanna 53 Problem Solvable Single Gate Match ondition! Is it feasible?! esign a single gate for match comparison " irst, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem?! What look like built out of nand2 gates and inverters? Penn ESE 370 all Khanna 54 Penn ESE 370 all Khanna 55 9

10 Total Power! Static MOS: Knobs! What are the options and knobs we can turn? " P tot a( load +2 sc V 2 f+vi s (W/Le-Vt/(nkT/q! Ratioed Logic: " P tot a( load +2 sc V 2 f +p(v out =lowv 2 /R pon +(1-p(V out =lowvi s (W/Le-Vt/(nkT/q! What can we do to reduce power? Penn ESE 370 all Khanna 56 Penn ESE 370 all Khanna 57 esign Space imensions Gate! Topology! ( What gates might we build? " ( Gate choice, logical optimization " ( anin, fanout, ( Serial vs. parallel! Gate style / logic family " ( MOS, Ratioed (N load, P load! (E Transistor Sizing! ( Vdd! (G Vth Penn ESE 370 all Khanna 58 Penn ESE 370 all Khanna 59 Gate Gate! ( High fanin?! ( Serial-Parallel? Penn ESE 370 all Khanna 60 Penn ESE 370 all Khanna 61 10

11 ( Logic amily! onsiderations for each logic family? ( Logic amily! onsiderations for each logic family? " MOS " Ratioed with PMOS load " Ratioed with NMOS load! Ratioed Logic " Reduced loads result in lower switching power (P dyn $ " Increased static power Penn ESE 370 all Khanna 62 Penn ESE 370 all Khanna 63 (E Sizing (E Sizing! How do we want to size gates?! How do we want to size gates? " Sizing transistors up will reduce delay # " Reduces short circuit power # # E = V dd I peak t sc % 1& & % (( $ $ 2' ' " Increases dynamic power Penn ESE 370 all Khanna 64 Penn ESE 370 all Khanna 65 ( Reduce Vdd (G Increase V th?! What happens as reduce V? " Energy? " ynamic $ " Static $ " Switching elay? %! What is impact of increasing threshold on " ynamic Energy? $ " Leakage Energy? $ " elay? % & τ gd =Q/I=(V/I & I d =(µ OX /2(W/L(V gs -V TH 2 & τ gd impact? & τ gd α 1/V & τ gd =Q/I=(V/I & I ds =(ν sat OX (W(V gs -V TH -V ST /2 & Limit on Vdd? Penn ESE 370 all Khanna 66 Penn ESE 370 all Khanna 67 11

12 Ideas! Three components of power dmin! HW 7 due 4/5 " P tot = P static + P dyn + P sc! We know many things we can do to our circuits! esign space is large! Systematically identify dimensions! Identify continuum (trends tuning when possible! Watch tradeoffs " don t over-tune