Design of Analog Integrated Circuits


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1 Design of Analog Integrated Circuits Chapter 11: Introduction to Switched Capacitor Circuits Textbook Chapter General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4 SwitchedCapacitor Integrator 13.5 SwitchedCapacitor CommonMode Feedback 1
2 General Considerations (a) First phase: S 1 and S 2 on, S 3 off (b) Second phase: At t = t 0, S 1 and S 2 turn off and S 3 turns on (c) V out V in0 C 1 /C 2 2
3 General Considerations Switchedcapacitor amplifiers operate in two phases: Sampling and Amplification Clock needed in addition to analog input V in 3
4 MOSFETS as Switches Suppose V in = V DD M 1 is saturated and we have: dvout ncox W CH ( VDD Vout VTH ) dt 2 L Solving, 1 Vout VDD VTH ncox W 1 t 2C L V V H DD TH As t, V out V DD  V TH so NMOS cannot pull up to V DD 2 4
5 MOSFETS as Switches Similarly, PMOS transistor fails to operate as a switch if gate is grounded and drain senses an input voltage of V THP or less On resistance rises rapidly as input and output levels fall to V THP above ground 5
6 MOSFETS as Switches: Speed Considerations Sampling speed is determined by : switch onresistance and sampling capacitance Onresistance also depends on input level for both NMOS and PMOS 6
7 MOSFETS as Switches: Speed Considerations For high speed signals, NMOS and PMOS switches must turn off simultaneously to avoid ambiguity in sampled value For moderate precision, circuit below is used to provide complementary clocks 7
8 MOSFETS as Switches: Precision Considerations Speed trades with precision Channel Charge Injection: Assuming V in V out, total charge in the inversion layer is Q WLC ( V V V ) ch ox DD in TH Charge injected to the right deposited on C H, introducing error in voltage stored on capacitor For half of Q ch injected onto C H, error (negative pedestal) equals WLCox V ( VDD Vin VTH ) 2C H 8
9 MOSFETS as Switches: Precision Considerations If all of the charge is deposited on C H, V WLC V V V ox DD in TH out Vin Vin 1 CH WLC CH ox WLC C H ox V DD V TH Since we assume Q ch is a linear function of V in, circuit exhibits only gain error and dc offset 9
10 MOSFETS as Switches: Precision Considerations Clock Feedthrough: MOS switch couples clock transitions through C GD or C GS Sampled output voltage has a constant offset WCov V VCK WC C C ov is the overlap capacitance per unit width ov H 10
11 MOSFETS as Switches: Precision Considerations kt/c Noise: On resistance of switch introduces thermal noise at output which is stored on the capacitor when switch turns off RMS voltage of sampled noise is still approximately equal to kt C 11
12 Charge Injection Cancellation Charge injected by main transistor removed by a dummy transistor M 2 M 2 is driven by so that after M 1 turns off and M 2 turns on, channel charge deposited by M 1 on C H is absorbed by M 2 to create a channel If W 2 = 0.5W 1, then charge injected by M 1, q 1 is equal to that absorbed by M 2 W1L 1Cox q1 ( VCK Vin VTHN ) 2 q W L C ( V V V ) ox CK in THN 12
13 Clockfeedthrough Cancellation If W 2 = 0.5W 1 and L 2 = L 1, effect of clock feedthrough is suppressed Total change in V out is zero because W C 2W C VCK V W C C W C W C C W C 1 ov 2 ov CK 1 ov H 2 2 ov 1 ov H 2 2 ov 0 13
14 Charge Injection Cancellation Charge injection appears as a commonmode disturbance, may be countered by differential operation q 1 = q 2 only if V in1 = V in2, thus overall error is not suppressed for differential signals V in1 = +V in +V CM, V in2 = V in +V CM ) Removes constant offset and nonlinear component q q WLC [( V V ) ( V V )] 1 2 ox in2 in1 TH 2 TH1 WLC [( V V ) 2 V 2 V ] ox in2 in1 F in2 F in1 14
15 UnityGain Sampler/ Buffer For discretetime applications, an unitygain amplifier [Fig. (a)] requires a sampling circuit [Fig. (b)] Accuracy limited by inputdependent charge injected by S 1 onto C H Another buffer A Another 15
16 UnityGain Sampler/ Buffer S 2 turns off slightly before S 1 during transition from sampling mode to amplification mode Charge injected by S 2, q 2 is inputindependent and constant, producing only an offset q 2 /C H After S 2 turns off, total charge at node X stays constant And charge injected by S 1 (S 3 ) does not affect output voltage 16
17 UnityGain Sampler/ Buffer (b): If V in =0 and q 2 =0, and S 1 turns off to inject a charge of q 1. C V ( V V ) C q 0 X X X out H If V in =0 and q 2 0, 2 V V / A V C / A ( V / A V ) C 0 X out v1 out X v1 out v1 out H V out 0 C V ( V V ) C q X X X out H 2 V V / A V C / A ( V / A V ) C q X out v1 out X v1 out v1 out H 2 V q / C if A 1 out 2 H v1 17
18 UnityGain Sampler/ Buffer Inputindependent charge injected by S 2 and S 2 can be cancelled by differential operation as shown Charge injection mismatch between S 2 and S 2 resolved by adding another switch S eq that turns off slightly after S 2 and S 2, equalizing the charge at nodes X and Y 18
19 19 UnityGain Sampler/ Buffer Precision Considerations: Assume opamp has a finite input capacitance C in A gain error of (C in /C H + 1)/A v H in v H in v out v out X X H X in H out C C A V C C A V V A V V V C V C V C V
20 UnityGain Sampler/ Buffer Speed Considerations: In sampling mode, circuit appears as in Fig. (a) Use equivalent circuit of Fig. (b) to find time constant in sampling mode Total resistance in series with C H is R on1 and the resistance between X and ground, R X V R R 1 1 R ( R ) C X 0 on2 X sam on1 H I X 1 GmR0 Gm Gm 20
21 UnityGain Sampler/ Buffer Consider circuit as it enters amplification mode Circuit must begin with V out 0 and eventually produce V out V 0 For relatively small C in, voltages across C L and C H do not change instantaneously so that V X = V 0 at the beginning of amplification 21
22 UnityGain Sampler/ Buffer Represent charge on C H by a voltage source V S that goes from zero to V 0 at t = t 0, while C H carries no charge itself The transfer function V out (s)/v S (s) can be obtained as V Gm C out ins CH s V C C C C C C s G C S L in in H H L m H This response is characterized by a time constant independent of opamp output resistance amp C L C in C G in m C C H H C H C L 22
23 Bottomplate Sampling The parasitic capacitance of C H at node X and a finite input capacitance C in lead to a gain error How to reduce the parasitic capacitance of C H at node X The bottom of C H is driven by input signal and the top is connected to the node X 23
24 Noninverting Amplifier In noninverting amplifier, in sampling mode, S 1 and S 2 are on while S 3 is off In amplifying mode, S 1 /S 2 turns off and S 3 turns on 24
25 Noninverting Amplifier S 2 turns off slightly before S 1 during transition from sampling mode to amplification mode. Total charge at X is constant ΔV P =q 1 /C 1 and when S 3 turns on, V P drops to zero And charge injected by S 1 does not affect output voltage 25
26 Differential Noninverting Amplifier S 2 turns off slightly before S 1. Input may change significantly without introducing any error. The sampling instant is defined by the turnoff of S 2. Total charge at X is constant and the final voltage free from errors of S 1 and S 3. 26
27 Noninverting Amplifier Precision Considerations: Assume opamp has a finite input capacitance C in Vout C1 C 1 C1 C2 C 1 in 1 Vin C2 1 Av 1C1 C2 Cin C 2 C2 A v1 A gain error increases with the noninverting gain of C 1 /C 2 C2 The feedback factor C of the noninverting 1C2 Cin CH amp. Is less than that of the unitygain buffer C C H in 27
28 Noninverting Amplifier Speed Considerations: In amplification mode, circuit appears as in Fig. (a) Use equivalent circuit of Fig. (b) to find time constant C C C eq in 1 The smaller feedback factor, the larger the time constant is; i.e., lower speed 28
29 Precision MultiplybyTwo Circuit Incorporates two equal capacitors C 1 = C 2 = C In sampling mode [Fig. (b)], voltage across C 1 and C 2 is V in Final voltage across C 1 is 2V in0 C2 The feedback factor is also, but higher? C C C 1 2 in 29
30 SwitchedCapacitor Integrator In sampling mode [Fig. (b)], S 1 and S 3 are on, S 2 and S 4 are off, allowing voltage across C 1 to track V in while op amp and C 2 hold previous value In the transition to integration mode, S 3 turns off first, injecting a constant charge onto C 1, S 1 turns off next, and subsequently S 2 and S 4 turn on Charge stored on C 1 is transferred to C 2 through the virtual ground node 30
31 SwitchedCapacitor CMFB In the reset mode, one plate of C 1 and C 2 is switched to V CM while the other is connected to the gate of M 6 Each capacitor sustains a voltage of V CM V GS6 In the amplification mode, S 2 and S 3 are on and the other switches are off, yielding an output CM level of V CM V GS6 + V GS5, which is equal to V CM if I D3 and I D4 are copied properly from I REF so that V GS5 = V GS6 31
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