MOS SWITCHING CIRCUITS

Transcription

1 ontent MOS SWIHING IRUIS nmos Inverter nmos Logic Functions MOS Inverter UNBUFFR MOS LOGI BUFFR MOS LOGI A antoni 010igital Switching 1

2 MOS Inverters V V V V V R Pull Up Pu Pu Pu Pull own G B Pd Pd Pd S QP Resistor requires large area and gives R transient responses Input low turns pull down switch offandtheoutputishigh. Input High the output is LOW. he lower transistor is turned ON andtheoutputispulledlow V OH <V -V N H noise margin low issipates power when output Low No power dissipation when output High nmos Good size ompromise between noise margin and speed issipates power when output Low No power dissipation when output High MOS ontrolled pull up and pull down. liminates the compromise between speed and noise margin Has no power dissipation in steady state H and L A antoni 010igital Switching

3 nmos Inverter graphical analysis V Q 1 k N WN µ ε = L t N e ox ox I S V GS = 0 V S Q V O epletion Mode F V I I S I S V = V I I S V I epletion F Load Line V > V GS N V OL V V S nhancement Mode F V S A antoni 010igital Switching 3

4 nmos Inverter mathematical analysis High V OH = V LOW ( ) ( ) ( V ) N VOL = V VN ± V VN kn kn hreshold V N Note that the LOW output voltage VOL depends on the ratio depends on the inverter pull-up ratio W pd L pu k L W n pd m = = = pu kn W L pd pu W pd esign involves a tradeoff between noise margin, switching speed and power dissipation. his is a disadvantage of ratioed logic when compared to MOS logic.helargerthepull-upratiom,thelowervol. Why? L pu A antoni 010igital Switching 4

5 nmos Inverter V V Q 1 i () PU t v () t i () P t v () t Q Rise ime depends on the pull up device Fall ime depends on the pull down device A antoni 010igital Switching 5

6 VN = 1V VN 4 nmos Inverter Aspecificnumericalexamplewiththefollowingparameters;V =5V = V k = 4k = 50 µ A/V, k n hus m = = 4 and V OL = 0.54 kn Low noise margin is? V V = = 0.46V N n OL n ( ) ( ) ( V ) N VOL = V VN ± V VN kn kn Smallest area is obtained by making (minimum feature size is set by L) L = W k = 1 pd pd n hen W pd = W pu is set to the minimum achievable line width for the particular technology of interest, for example to 0. µm for 0. micron technology. Since kn k n = then Lpu = 4 4 Given L min can achieve Lpu = 4Lmin Wpu = Lmin W pu V Q 1 W L pu pu = 1 4 Q Wpd = 1 L pd A antoni 010igital Switching 6

7 nmos Logic Structure used to realise Logic functions in nmos V I 1 IM PULL OWN NWORK Y he pull down network is characterised by a transmission function,, that indicates whether there is a path through the network. he network is as series and parallel combination of enhancement mode Fs. =1 if there is a conduction path between ground and the output.ywillbelow. =0 if there is an open circuit between the output and groundviathepulldownnetwork.ywillbehigh. he input to output function is determined by the transmission function : Y Y = 0 when = 1 Y = = 1 when = 0 A antoni 010igital Switching 7

8 nmos Logic xample V he transmission function for the pull down = ( A B) + + ( F) Y Q Pathexists fromyto0: A Q A IfAandBarebothhighandturnonQ A andq B Q Q OR IfhightoturnonQ B Q B F Q F OR If,andFareallhighandturnonQ A Q B andq F Y = ( A B) + + ( F) A antoni 010igital Switching 8

9 nmos Sizing 1.onsiderworstcaseforV OL (highestvalue). his occurs when only one branch is conducting at a time. If more than one branch conducts, V OL is lower higher noise margin which is not a problem.. For each branch in the pull down network to give the same V OL when it alone is conducting,eachbranchmusthavethesameresistance,r=r ON,intheONstate. V 3.onsiderthecentrebranch,whentheleftandrightbranchesarenot conducting, the circuit reduces to an inverter: A B F Y Minimum area is obtained by making m k n = 4 = kn W pd = W pu for V OL = 0.54 k 1 W n pu k = = = L = 4W 4 4 L n pu pu pu L = W k = 1 pd pd and an acceptable noise margin n A antoni 010igital Switching 9

10 nmos Sizing 4. I for a MOSF is proportional to the ratio Ohmic region incremental resistance R in the is W L 1 R W L A V Y 5. onsider the left hand branch ( transistors in series). For the total resistance to be the same as for the branch, then each transistor musthavearesistanceof R/andthus: W. = L B F 6. he right branch has three transistors in series thus to achieve the same pull down resistance as the branch that has one need: W = 3 L A antoni 010igital Switching 10

11 nmos xample V W = 1 L 4 Z A B R R W = L W L = W =1 L R F W = 3 L W =3 L W =3 L R 3 R 3 R 3 R ot1 R R = + = R Rot = R Rot1 R R R = + + = R A antoni 010igital Switching 11

12 MOS Inverter V I G G i P i N V S S P v o N V I V O V n + n + p + p + p- well n-substrate A antoni 010igital Switching 1

13 N hannel F Ohmic Region: n channel p channel 1 IN = k N VGSN VN VSN V 1 I = k ( V V ) V V ( ) SN P P GSP P SP SP Saturation: n channel p channel k W µ ε I = ( V V ) k = N N e ox N GSN N N LN tox kp WP µ ε IP = ( VGSP VP) kp = L t P h ox ox Since µ h ½ µ e, then k P ½ k n for the same W/L ratio. o achieve the same value of k as an n channel device, ( for the same length channel), a p-channel transistor needs to be twice as big an n- channel transistor. oes not affect noise margin but switching speed. A antoni 010igital Switching 13

14 MOS Inverter onsider initially the case of perfectly matched complementary ideal p and n devicesinthemosinverter& V >V V o N OFF N SAURA P OHMI V V V k k k W L W L n N = P = = N = P = n p p u u e h M A V ' V O = V i G S N SAURA P SAURA N OHMI P SAURA v i i P i N G P N v o P OFF S B V V i A antoni 010igital Switching 14

15 Unbuffered MOS GAS he generic structure for unbuffered MOS logic V Input vector (x, y, z, I) p-net N P n-net N N p-channel transistors Output f n-channel transistors ransmission function P ransmission function N P N = 1 Output = 1 = = 0 ( V ) P N = 0 = 0 not allowed: floating output. P N = 0 Output = 0 = = 1 ( GN) P N = 1 = 1 notallowed,currentfromv toground. omplementary No Steady urrent and Valid Output A antoni 010igital Switching 15

16 Unbuffered MOS GAS he generic structure for unbuffered MOS logic V Input vector (x, y, z, I) p-net N P n-net N N p-channel transistors Output f n-channel transistors ransmission function P ransmission function N herefore to realise the logic function f( x, y, z,..) N = f( x, y, z,..) = P N Since nmos transistors are turned ON by a HIGH input: N = f ( x,.. ) SincepMOStransistorsareturnedONbyaLOWinput: = f ( x,... ) P A antoni 010igital Switching 16

17 Unbuffered MOS GAS x V z y f f( x, y, z) = x + yz ( ) ( ) = f( x, y, z,..) = x+ yz = x yz = x y+ z N x y (,,,..) z P = f x y z = x+ yz Network characteristics: n and p channel always paired A antoni 010igital Switching 17

18 Unbuffered MOS GAS Logic function? Positive logic NOR Gate V A B 4 f 3 1 Is the incremental output resistance a function of the inputs or only a function of the output state? A antoni 010igital Switching 18

19 Unbuffered MOS GAS Logic function? Positive logic NAN Gate V 4 f = A B A 3 B 1 Is the incremental output resistance a function of the inputs or only a function of the output state? A antoni 010igital Switching 19

20 Unbuffered MOS GAS he output resistance changes is a function of the combination of the inputs. Output transient times change as a function of the of the combination of the inputs. he input thresholds for each input is a function of the combination of the other inputs. A antoni 010igital Switching 0

21 Buffered MOS input vector (x, y, z, I) p-net N P n-net N N G G S V G G S S S Is the incremental output resistance a function of the inputs or only a function of the output state? Is there additional propagation delay? A antoni 010igital Switching 1

22 iodes in MOS Structures V I V O V p + n + n + p + p + n Some diodes in MOS structures are created to protect MOS devices from over voltage while others are inherent. A common source of over voltage is lectrostatic ischarge from humans(s). A antoni 010igital Switching

23 iodes in MOS Structures S G 1 3 V 5 G 4 S A antoni 010igital Switching 3

24 MOSF apacitances Operating Region GB GS G OLS OL utoff W L 0 0 W L W L ox eff ox ox riode 0 ox W Leff ox W L eff W L W L ox ox Saturated 0 ( ) ox W L eff 0 ox W L ox W L 3 Source Gate rain OLS GS G OL SB GB B otal gate capacitance = G GS G GB OLS OL A antoni 010igital Switching 4

25 quivalent Load apacitance O A I Gp Bp A I Gn V Line v() t 1 Bn Line O = + + f(, ) Bn Bp Gn Gp V We assume that the capacitances are constant and independent of voltage. Gp he input source is assumed to switch rapidly from 0 to Vcc. he output will thenswitchfromvccto0 v() t 1 i Gn 0 v () o t A antoni 010igital Switching 5

26 i() t i() t ( Gn + Gp) i() t V v () o t v o (0) = V v(0) = 0 1 v ( ) = 0 v( ) = V o ( Gn Gp) 1 ( () ()) 1 o i() t dt = + dt ( Gn Gp) i() t = ( () ()) d v t v t d v t v t ( Gn Gp) ( 1( ) o( )) ( 1(0) o(0) ) Q = + v v v v v 1 () t = ( + ) ( ) = ( + ) 1 Q V V V dt dt Gn Gp Gn Gp We define an equivalent capacitor, eq, at the output node which involves the same total charge transfer for same voltage change. o Similar to Miller ffect for a gain =1 ( ) Q Q = = = + eq Gn Gp vo V ( ) = + + f(, ) = O Bn Bp Gn Gp Bn Bp Gn Gp A antoni 010igital Switching 6

27 MOS Switching he channel is induced almost instantaneously and current flow is then by drift transport of majority carriers in an electric field, similar to current in a resistor. Since there are no minority carriers involved there are no chargestorageeffectsasinabj. Withfast switchinginput, the MOS device is modelled as an instantaneously switched voltage-controlled device. he larger the load the more accurate the approximation (Why?). he ideal voltage drive is also critical to this approximation. o urrent flows during switching. A antoni 010igital Switching 7

28 MOS Switching G S V V V V, 0pt τ o 1 V 0V t = 0 v i i P i N G S P N I O v o he n channel F is in the saturated region and the p channel is OFF V p V V, τ < t o 1 he n channel F is in theohmicregionandthep channel is OFF. A antoni 010igital Switching 8

29 MOS Switching V i V t V N Saturated V V N Ohmic I t=0 V V V o τ 1 I V V pv V o I 1 ( ) = k V V I = k ( V V ) V 1 V o o A antoni 010igital Switching 9

30 MOS Switching V V V V, 0pt τ o 1 t=0 I = 1 k V V ( ) I V o dv dt o = I [ τ ] I ( t τ ) = V () t V ( ) 0 o o o ( t τ ) = o [ o() o( τo) ] ( ) V t V k V V t = τ = 1 and τo 0 V 1 τ = ( ) k V V A antoni 010igital Switching 30

31 I V V pv V o MOS Switching V pv V, τ < t o 1 I = k ( V V ) V 1 V o o dv 1 I = = k ( V V ) V V dt o o o ( t τ ) = 1 Vo( t) V o ( τ ) 1 1 k ( V V) V V dv ( V V ) 1 Vo() t ( t τ1) = ln k( V ) V ( V V ) 1 Vo( τ1) A antoni 010igital Switching 31

32 10-90% Fall ime V V V 1 V 10 9 V 10 t τ τ = ( τ τ ) + ( τ τ ) kv kv 3.7 kv τ o τ 1 τ hecalculationoftheriseimefollowsthesamelines - different k. If k is the same for both p and n channel devices then theriseandfalltransientsarethesame. A antoni 010igital Switching 3

33 Buffered MOS V input vector (x, y, z, ) p-net N P f ( x% ) G S G S n-net N N G G S S lose to symmetric output drive capacity for high and low onsistent switching times for l->h and H->L Low variation in input "threshold" to the state of other inputs A antoni 010igital Switching 33

34 Power issipation Shoot-hrough urrents between supply rails during switching. ynamic Power onsumption harging and ischarging apacitors Leakage currents through diodes and transistors A antoni 010igital Switching 34

35 Power issipation V o V o N OFF A N SAURA P OHMI ' N SAURA P SAURA N OHMI P SAURA P OFF V I V V ( V V ) A antoni 010igital Switching 35

36 Power issipation V V V I V I PK tr = 1 f tf IPK tsw PAV SW = V IAV SW = V f = VIPKtswf t = t = t SW r f A antoni 010igital Switching 36

37 Power issipation ynamic Power onsumption harging and ischarging apacitors P = V L f Leaking currents through diodes and transistors P = V I S otal Power P = V I t f + V f + V I PK sw L P P V f V I = ( P + L) + is determined by fitting the above equation to measured data "power dissipation capacitance A antoni 010igital Switching 37