Introduction to Computer Engineering ECE 203
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1 Introduction to Computer Engineering ECE 203 Northwestern University Department of Electrical Engineering and Computer Science Teacher: Robert Dick Office: L477 Tech Phone: Webpage: dickrp/ece203 Teaching Assistants Zhènyǔ Gù (L470) Debasish Das (M314) 1
2 Homework index 1 Reading assignment
3 Today s goals Adminstrative stuff Review Combinational logic design example Understand switch model and CMOS Be capable of manipulating Boolean formulas 3
4 Possible grading scheme 15% homeworks 35% labs 20% midterm exam 30% final exam 4
5 Grading Some requested additional homework weight 20% homeworks 35% labs 18% midterm exam 27% final exam 5
6 Planned schedule Mondays: Labs assigned and collected Wednesdays: Homeworks collected and assigned Friday s class will normally focus on the lab and homework of the week, and will be given by Zhènyǔ Gù 6
7 Review What is a truth table? Combinational vs. sequential logic? Symbol and notation for AND, OR, NOT? Other gates also exist, e.g., NAND, NOR, XOR, XNOR 7
8 Case study of simple combinational logic design Seven-segment display Given: A four-bit binary input Display a decimal digit ranging from zero to nine Use a seven-segment display 8
9 Case study of simple combinational logic design Seven-segment display Given: A four-bit binary input Display a decimal digit ranging from zero to nine Use a seven-segment display L1 L4 L6 L2 L5 L7 L3 9
10 Case study Seven-segment i 3 i 2 i 1 i 0 dec
11 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
12 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
13 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
14 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
15 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
16 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
17 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
18 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
19 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
20 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
21 Case study Seven-segment L4 L5 L1 L2 L3 L6 L7 i 3 i 2 i 1 i 0 dec L1 L2 L3 L4 L5 L6 L
22 Implement L4 i 3 i 2 i 1 i 0 dec L
23 L4 implementation i 3 i 0 i 1 i 0 i 2 L4 i 1 i 2 In a future lecture, I ll explain how to do this sort of design. 23
24 L4 implementation i 3 i 0 i 1 i 0 i 2 L4 i 1 i 2 In a future lecture, I ll explain how to do this sort of design. 24
25 Switch-based design representation A switch shorts or opens two points dependant on a control signal Used as models for digital transistors Why is using normally open and normally closed particularly useful for CMOS? NMOS and PMOS transistors easy to model 25
26 Switch-based design representation A switch shorts or opens two points dependant on a control signal Used as models for digital transistors Why is using normally open and normally closed particularly useful for CMOS? NMOS and PMOS transistors easy to model 26
27 Switch-based definitions true true control closed switch control open switch normally open switch false normally closed switch false open switch closed switch 27
28 Microwave control example at least five minutes elapsed water vapor sensed true cancel button pressed halt microwave What happens if the cancel button is not pressed and five minutes haven t yet passed? The output value is undefined. 28
29 Microwave control example at least five minutes elapsed water vapor sensed true cancel button pressed halt microwave What happens if the cancel button is not pressed and five minutes haven t yet passed? The output value is undefined. 29
30 Constraints on network output Under all possible combinations of input values Each output must be connected to an input value No output may be connected to conflicting input values 30
31 Switch-based AND a b false output true Note that this requires Normally closed switches that transmit false signals well Normally open switches that transmit true signals well 31
32 Switch-based AND a b false output true Note that this requires Normally closed switches that transmit false signals well Normally open switches that transmit true signals well 32
33 Relationship with CMOS Metal Oxide Semiconductor Positive and negative carriers Complimentary MOS PMOS gates are like normally closed switches that are good at transmitting only true (high) signals NMOS gates are like normally open switches that are good at transmitting only false (low) signals 33
34 Relationship with CMOS Metal Oxide Semiconductor Positive and negative carriers Complimentary MOS PMOS gates are like normally closed switches that are good at transmitting only true (high) signals NMOS gates are like normally open switches that are good at transmitting only false (low) signals 34
35 Relationship with CMOS Metal Oxide Semiconductor Positive and negative carriers Complimentary MOS PMOS gates are like normally closed switches that are good at transmitting only true (high) signals NMOS gates are like normally open switches that are good at transmitting only false (low) signals 35
36 NAND gate Therefore, NAND and NOR gates are used in CMOS design instead of AND and OR gates a b true output false = 36
37 NAND gate Therefore, NAND and NOR gates are used in CMOS design instead of AND and OR gates true a PMOS b output false NMOS = 37
38 Transistors Basic device in NMOS and PMOS (CMOS) technologies Can be used to construct any logic gate 38
39 NMOS transistor source (N) gate oxide silicon bulk (P) drain (N) 39
40 NMOS transistor source (N) gate oxide channel silicon bulk (P) drain (N) 40
41 NMOS transistor Metal oxide semiconductor (MOS) Now, it s actually polysilicon oxide semiconductor P-type bulk silicon doped with positively charged ions N-type diffusion regions doped with negatively charged ions Gate can be used to pull a few electrons near the oxide Forms channel region, conduction from source to drain starts 41
42 CMOS NMOS turns on when the gate is high PMOS just like NMOS, with N and P regions swapped PMOS turns on when the gate is low NMOS good at conducting low (0s) PMOS good at conducting high (1s) Use NMOS and PMOS transistors together to build circuits Complementary metal oxide silicon (CMOS) 42
43 CMOS NAND gate V DD A B Z V SS 43
44 CMOS NAND gate PMOS V DD A B Z NMOS V SS 44
45 CMOS NAND gate V DD A B Z V SS 45
46 CMOS NAND gate pull up network V DD A B Z V SS pull down network 46
47 CMOS NAND gate layout V DD a z b V SS 47
48 CMOS inverter operation V DD A B V SS 48
49 CMOS inverter operation V DD A A=0 B=1 B V SS 49
50 CMOS inverter operation V DD A B V SS 50
51 CMOS inverter operation V DD A A=1 B B=0 V SS 51
52 NAND operation V DD A B Z V SS 52
53 NAND operation A A=0 Z=1 V DD B=0 B Z V SS 53
54 NAND operation V DD A B Z V SS 54
55 NAND operation V DD A A=0 Z=1 B Z B=1 blocked V SS 55
56 NAND operation V DD A B Z V SS 56
57 NAND operation A Z=1 V DD B=0 B Z blocked A=1 V SS 57
58 NAND operation V DD A B Z V SS 58
59 NAND operation V DD A Z=0 B Z B=1 A=1 V SS 59
60 NOR operation V DD Z A B V SS 60
61 NOR operation A=0 V DD Z B=0 A Z=1 B V SS 61
62 NOR operation V DD Z A B V SS 62
63 NOR operation V DD A=0 blocked Z A Z=0 B B=1 V SS 63
64 NOR operation V DD Z A B V SS 64
65 NOR operation blocked V DD Z B=0 A A=1 Z=0 B V SS 65
66 NOR operation V DD Z A B V SS 66
67 NOR operation V DD Z A Z=0 B A=1 B=1 V SS 67
68 Threshold effect on NMOS/PMOS transistors Recall that NMOS transmits low values easily transmits high values poorly PMOS transmits high values easily transmits low values poorly This is due to the effect of the transistors thresholds 68
69 Threshold effect on NMOS/PMOS transistors V T, or threshold voltage, is commonly 0.7 V NMOS conducts when V GS > V T PMOS conducts when V GS < V T What happens if an NMOS transistor s source is high? Or a PMOS transistor s source is low? Alternatively, if one states that V TN = 0.7 V and V TP = 0.7 V then NMOS conducts when V GS > V TN and PMOS conducts when V GS < V TP 69
70 NMOS transistor source (N) gate oxide silicon bulk (P) drain (N) 70
71 Threshold effect on NMOS/PMOS transistors If an NMOS transistor s input were V DD (high), for V GS > V TN, the gate would require a higher voltage than V DD If an PMOS transistor s input were V SS (low), for V GS < V TP, the gate would require a lower voltage than V SS 71
72 Implications of threshold V DD A B Z V SS NAND/NOR easy to build in CMOS 72
73 Implications of threshold AND/OR requires more area, power, time 73
74 CMOS transmission gates (switches) NMOS is good at transmitting 0s Bad at transmitting 1s PMOS is good at transmitting 1s Bad at transmitting 0s To build a switch, use both: CMOS 74
75 CMOS transmission gate (TG) C A B C 75
76 CMOS transmission gate (TG) C C = 0 A B C = 1 C 76
77 CMOS transmission gate (TG) C C = 0 A B C = 1 C 77
78 CMOS transmission gate (TG) C C = 0 A B B = A C = 1 C 78
79 CMOS transmission gate (TG) C A B C 79
80 CMOS transmission gate (TG) C C = 1 A B C = 0 C 80
81 CMOS transmission gate (TG) C blocked A C = 1 B blocked C = 0 C 81
82 CMOS transmission gate (TG) C blocked A C = 1 B B =High-Z blocked C = 0 C 82
83 Other TG diagram C A B A C B C C 83
84 What can we build with TGs? Anything... try some examples. 84
85 Summary Administrative details Combinational logic design example Logic gates can be implemented with physical devices, e.g, CMOS Underlying technology influences higher-level representation NAND, NOR vs. AND, OR 85
86 Reading assignment M. M. Mano and C. R. Kime, Logic and Computer Design Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed., 2004 Section
87 Computer geek culture reference
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