3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
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1 Code No: RR Set No (a) Find g m and r ds for an n-channel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = V 1 (b) Explain the term Figure of merit of a MOS Transistor. [10+6] 2. (a) With neat sketches explain how resistors and capacitors are fabricated in p- well process. (b) With neat sketches explain how resistors and capacitors are fabricated in n- well process. [8+8] 3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C 4. Design a layout diagram for the CMOS logic shown below [16] Y = (A + B + C) 5. Calculate ON resistance from V DD to GND for the given inverter circuit shown in Figure 5, If n-channel sheet resistance is 10 4 Ω per square. [16] 1 of 2 Figure 5
2 Code No: RR Set No With neat sketch explain clearly the architecture of the PROM. [16] 7. With respect to synthesis process explain the following terms. (a) Flattening (b) Factoring. (c) Mapping. [6+5+5] 8. Mention different growth technologies of the thin oxides and explain about any one technique. [16] 2 of 2
3 Code No: RR Set No (a) Explain with neat sketches the Drain and Transfer characteristics of n-channel enhancement MOSFET. (b) With neat sketches explain the transfer characteristics of a CMOS inverter. [10+6] 2. (a) Compare between CMOS and bipolar technologies. (b) With neat sketches explain nmos fabrication process. [8+8] 3. Design a stick diagram for the NMOS logic shown below [16] Y = (A + B + C) 4. Design a layout diagram for nmos inverter. [16] 5. Calculate the gate capacitance value of 5µm technology minimum sized transistor with gate to channel capacitance value is pf/µm 2. [16] 6. (a) What are the advantages and disadvantages of the reconfiguration. (b) Mention different advantages of Anti fuse Technology. [8+8] 7. (a) What is the goal of VHDL synthesis step in design flow? (b) Explain how register transfer level description provides optimized synthesis netlist. [8+8] 8. Clearly explain the wire bonding technology of the die bonding. [16] 1 of 1
4 Code No: RR Set No (a) With neat sketches explain the formation of the inversion layer in P-channel Enhancement MOSFET. (b) An NMOS Transistor is operated in the triode region with the following parameters V GS = 4V ; V tn = 1V ; V DS = 2V ; W/L = 100; µncox = 90 µa/v 2. Find its drain current and drain source resistance. [8+8] 2. With neat sketches explain BICMOS fabrication in an p-well process. [16] 3. Design a stick diagram for the CMOS logic shown below [16] Y = (AB + CD) 4. Design a layout diagram for two input CMOS NOR gate. [16] 5. Calculate the gate capacitance value of 5µm technology minimum sized transistor with gate to channel capacitance value is pf/µm 2. [16] 6. With neat sketch explain clearly the architecture of the PROM. [16] 7. Mention about various types of simulators used in ASIC design flow and clearly discuss about the significance of each simulator. [16] 8. Explain clearly the molecular beam epitaxy method. [16] 1 of 1
5 Code No: RR Set No (a) With neat sketches explain the Drain characteristics of p-channel Enhancement MOSFET. (b) An p-mos Transistor is operated in the Active region with the following parameters V GS = 4.5V ; V tp = 1V ; W/L = 95; µncox = 95 µa/v 2. Find its drain current and drain source resistance. [8+8] 2. With neat sketches explain how Diodes and Resistors are fabricated in Bipolar process. [16] 3. Design a stick diagram for two input CMOS NAND and NOR gates. [16] 4. Design a layout diagram for the PMOS logic shown below [16] Y = (AB) + (CD) 5. Calculate ON resistance from V DD to GND for the given inverter circuit shown in Figure 5, If n-channel sheet resistance is 10 4 Ω per square. [16] Figure 5 6. Implement 2-bit comparator using PROM. [16] 7. What is need for RTL simulation? Clearly explain RTL simulation flow in the ASIC design flow and also mention few leading simulation tools. [16] 8. Explain about the following packaging design considerations. 1 of 2
6 Code No: RR Set No. 4 (a) Electrical considerations. (b) Mechanical design consideration. [8+8] 2 of 2
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