Semiconductor Memories

Transcription

1 Introduction Classification of Memory Devices "Combinational Logic" Read Write Memories Non Volatile RWM Read Only Memory Random Access Non-Random Access Static RAM FIFO Dynamic RAM LIFO Shift Register EPROM EEPROM FLASH Mask-programmed Programmable (PROM)

2 ROM (Read Only Memory) Linear Addressing m inputs (address A i = 2 m combinations) Linear, one-dimensional addressing Address lines A 0 A m 2 m decoder W 0 W Word-lines 2 m n ROM Encoder n outputs (data) memory core ROM Cell W j n n < > m m Memory matrix n = m A m 2 A m W M 2 W M m-bit address 2 m = M To Sense Amplifiers Dn D n 2 D D 0 n-bit data Data lines D i 2

3 ROM (Read Only Memory) ROM Cell ROM Cell The Cell is designed so that a 0 or is presented to the bit line D i upon activation of its word line W j. W j Diode-based ROM Cell MOSFET-based ROM Cell BJT-based ROM Cell D i 3

4 ROM (Read Only Memory) ROM Cell Diode-based ROM Cell ROM Cell W j 0 W j Passive cell device Cell content is 0 Current D i- D i Cell content is C Wj V D D i C Di- R C Di R V Di() V V = Wj( ) D Disadvantage of the diode cell : No isolation between the word line W j and the bit line D i. The W j driver must provide quite high current to charge capacitance C tot. ( And discharge C Wj ) This approach works only for small memories. C tot(max) C Wj + n i= C Di n = number of data bits 4

5 ROM (Read Only Memory) ROM Cell MOSFET-based ROM Cell ROM Cell Active cell device D i- V DD D i W j 0 W j Current Cell content is 0 G i D S Cell content is C Wj D i C Di- R C Di R V Di( ) V DD Word-line driver : Charge and discharge the word-line capacitance C Wj. NMOS transistor i : All output-driving current. Charge the bit-line capacitance C Di. "Source follower implementation" C tot(max) C Wj OR ROM 5

6 ROM (Read Only Memory) ROM Cell MOSFET-based ROM Cell ROM Cell Active cell device V DD W j 0 Pull-up devices V DD D i- D i NMOS Current D i W j Cell content is G D Cell content is 0 C Wj Word-line driver : i S Charge and discharge the word-line capacitance C Wj. C Di- C Di NMOS transistor i : Discharge the bit-line capacitance C Di. Good isolation between word and bit line V Di( ) V DD "Pull-down device implementation" Default value of the output is V Di( 0 ) 0 NOR ROM 6

7 ROM (Read Only Memory) ROM Cell 2 m multiple-emiter transistors if linear addressing is used. BJT-based ROM Cell Used in early bipolar roms D 0 D D 2 D 3 W j W j W j+ V DD W j+ Mask programmable connections W j+2 W j+3 V DD W j+2 Multiple Emitter Transistor D W 0 j+3 D D 2 R OR ROM 7

8 ROM (Read Only Memory) Programming the ROM Cell Think about mass-production Only one mask layer, the contact mask, is used to program the memory array. NOR ROM The precence of a metal contact to the bit line creates a 0-cell, while its absence indicate a -cell. Threshold programming NOR ROM The threshold (V TO ) of the transistor (-cell) is selectively raised to value higher than the voltage swing of the word line W j. (V TO = 7V for 5V supply voltage) 8

9 ROM (Read Only Memory) One-dimensional addressing A 0 A m-bit address m m 2 decoder W 0 W short Memory matrix long if m is large Aspect ratio of the memory is not close to the unity. Problems The shape of storage array is an unacceptable. A m 2 A m W M 2 W M m 2 = M D7 D6 D D 0 8-bit data An example of one-dimensional addressing Solution is 2-dimensional addressing Aspect ratio of the memory is close to the unity. Smaller decoders. X Y 9

10 ROM (Read Only Memory) Two-dimensional addressing An example of 2048 bit ROM (52x4 organization) The number of word lines m K 2 Bit line 2 6 = 64 The number of word lines W 0 2k-bit memory A K A m- Row decoder Storage Cell Word line A 0 A 5 Row decoder W X 32 matrix The number of bit lines = 4 8 = 32 A 0 A K- Sense Amps/Drivers Column decoder K N 2 K N 2 N Output bits A 6 A 7 A 8 CS Sense Amps/Drivers 8X 8X 8X 8X Four 8X Multiplexers 4 Output bits D N- - D 0 D 3 D 2 D D 0 0

11 ROM (Read Only Memory) Word Expansion Two 52 X 4-bit ROM One 52 X 8-bit ROM A8 - A0 A8 - A0 A8 - A0 52X4 52X4 CS D3 - D0 CS D3 - D0 D7 D4 D3 D0

12 ROM (Read Only Memory) Address Expansion A8 - A0 A9 A0 2-to-4 decoder 0 CS A8 - A0 52X4 D3 - D0 CS A8 - A0 52X4 D3 - D0 CS A8 - A0 52X4 D3 - D0 CS A8 - A0 52X4 D3 - D0 3 "Glue logic" 2kX4-bit Address space D0 D D2 D3 2

13 ROM (Read Only Memory) Applications Look-up Tables Sequence Generators Waveform Generators Character Generators Stored Programs Combinational Logic 3

14 Nonvolatile Read-Write Memories Programmable ROMS (PROMS) Introduction Write Once device : OTP ROM (One Time Programmable) PROM Cell structure allows the customer to program the memory one time. This is most often accomplished by introducing fuses in the memory cell. (nichrome, polysilicon, or other conductors) UV EPROM (NVRW memory) without erasing window. Cheap plastic package. 4

15 Nonvolatile Read-Write Memories Programmable ROMS (PROMS) Introduction Several Times Writable : NVRW memories (Nonvolatile Read-Write Memories) NVRW memories The memory core consists of an array of modified transistors which are programmed by selectively disabling or enabling some of them. The threshold of the transistor is altered electrically. The memory must be erased before next programming round. The Floating-Gate Transistor 5

16 Nonvolatile Read-Write Memories Memory Cell Type (FAMOS) Floating-gate Avalanche-injection MOS The structure is similar to a traditional MOS device, except that an extra polysilicon strip is inserted between the gate and channel. Programming FLOATING GATE SiO 2 GATE 20V 20V Electrons are trapped D on the floating gate. G It results in higher V TO S Source + n Substrate p t ox t ox Drain + n Erasing Device cross-section of the FAMOS Schematic Symbol UV light 6

17 Nonvolatile Read-Write Memories Erasable-Programmable ROM (EPROM) EPROM is erased by shining ultraviolet light on the Cells through the transparent window in the package. Cell Array UV-EPROM Pin Pin 40 Typical programming time : 5 0 µ s/word Erase/Write cycles is generally limited to a maximum of one thousand. Mainly because of UV erasing. "Off-system" erasure procedure. Erasing takes time typically up to hour. Ceramic Packages Pin Configuration The example UV-EPROM chip 7

18 Nonvolatile Read-Write Memories Memory Cell Type (FLOTOX) Electrically-Erasable-Programmable ROM (EEPROM, E2PROM) FLOATING GATE SiO 2 GATE Source Drain 20 30nm The number of Erasing and Programming cycle is limited + n p Substrate FLOTOX transistor 0nm + n Schematic Symbol 8

19 Read-Write Memories Introduction Memory access time Read and Write time : Independent of memory location. Memory cycle time Minimum interval of time reguired between successive memory operations. Static RAM Static memory cell R S Basic Storage Cells NMOS CMOS Volatile Large dimensions Nonvolatile Local Power Supply Inside the package Dynamic RAM Dynamic memory cell Needs refreshing Basic one-transistor cell C S 9

20 Read-Write Memories Static RAM Cell Assumption : Linear selection X Address Write Data In Write Enable S Read Data Out R Write Operation : Write Data In Write Enable X Address 0 S R 0 Read Data Out 0 Read Operation : Set X Address to. 20

21 Read-Write Memories Static RAM Cell Linear selection X i +V CC Write Data In DI Write Enable WE X Address S R OC Read Data Out DO Address Lines nxm dec. DI WE DO m x organized RAM 2

22 Read-Write Memories Static RAM Cell + V DD + V DD S R S R R S NMOS NOR gates R S CMOS NOR gates 22

23 Read-Write Memories Static RAM Cell The 6-MOS Memory Cell + V DD Xi Xi To R/W=0 of all cells in column j To R/W= of all cells in column j X i X i A static CMOS memory cell 23

24 Read-Write Memories Static RAM Cell 2-dimensional addressing of RAM Cell X 0 0-bit line for column -bit line for column A0-A6 7-to-28 row decoder X X To R/W 0 amplifiers Y 0 Y Y 27 7-to-28 column decoder To R/W amplifiers A7-A3 24

25 Read-Write Memories Static RAM Cell 0-bit dataline -bit dataline 2-dimensional addressing of RAM Cell Storage Cell (-) containing 6 NMOS transistors X RAM Cell (-) 0-bit data line To R/W=0 of all cells in column X + V DD N N -bit data line X To R/W= of all cells in column 7,9, Write 0 WE Write 7,0, 2 Y 3, 5, 4 6 Read 0 Read Write Write 9 0 W Y + V DD Read 0 Read 2 W R/W 0 amplifiers Millman fig. 9-2 R/W 7 R/W amplifiers 25

26 Read-Write Memories Static RAM Cell Cell contains a bit WE W S Write Enable Write ( Data Input, D in ) Sense ( Data Output, D out ) 0-bit data line To R/W=0 of all cells in column X + V DD N 3 N X -bit data line To R/W= of all cells in column Assumption : Cell contains a bit Y V DD 2 Conducts (ON) (OFF) VN VDD and VN 2 0V 5 6 Write Write 9 0 W Read 0 Read S S 2 W W R/W 0 amplifiers R/W WE 7 R/W amplifiers 26

27 Read-Write Memories Static RAM Cell Cell contains a bit 0 Assumption : Cell contains a bit 0 2 (OFF) Conducts (ON) 0-bit data line To R/W=0 of all cells in column + V DD N 3 N bit data line To R/W= of all cells in column VN 2 VDD and VN 0V X X Y V DD 5 6 Write Write 9 0 W Read 0 Read S 2 W R/W 0 amplifiers R/W WE 7 R/W amplifiers 27

28 Read-Write Memories Static RAM Cell The Read Cycle of the (-) RAM Cell (2-dimensional addressing) READ CYCLE WE = 0 Write 0 = Write = 7 ( OFF ) don' t care Due to the current through 8 and 4, the voltage drop over 2 is practicaly V DD. V GS4 0V (OFF) 4 X = Y = S = 0-bit data line To R/W=0 of all cells in column Zero Current X + V DD N 3 N X To R/W= of all cells in column Write 0 3 S=0 S= 4 Write W R/W 0 amplifiers R/W 0 WE=0 Y + V DD Read 0 Read off bit data line 2 W 0 Current to the Ground Voltage Drop over 2 R/W amplifiers 28

29 Read-Write Memories Static RAM Cell The Write (--) Cycle of the (-) RAM Cell (2-dimensional addressing) WRITE CYCLE X = Y = WE = and W =,W = 0 ( ) ( ON ) V 2 V N 0V = OFF N V DD End of WR-cycle X = Y = 0 WE = 0 ( OFF ) = = OFF ON Cell= ( to Cell ) 0-bit data line To R/W=0 of all cells in column Zero Current X + V DD N 3 N X To R/W= of all cells in column Write 0 3 S S 4 Write W=0 W on on off R/W 0 amplifiers R/W 0 WE= Y + V DD Read 0 Read on 7 0 Voltage Drop over 4 0 -bit data line 2 on WW= 0 Current to the Ground on R/W amplifiers Voltage Drop over 2 29

30 Read-Write Memories Dynamic RAM Cell WRITE CYCLE Xi = Yj = V One-MOSFET Dynamic RAM-Cell ( ) Write amplifier set the level of the data bit line Data bit line : ( ) V V ( ) V = C Data bit line : ( 0) V V ( 0) READ CYCLE V C = Xi = Yj = V ( ) Y j X i Data bit or Column line C C + C The read amplifier (sense amp.) detects the voltage level of the data bit line: V = VC C << 2 >> C V V 2 One data bit line Row line Basic one-transistor cell C C 2 To R/W amplifiers Where C2 is capacitance of the data bit line Read cycle destroys the content of memory cell Leackage current Refresh time ms Write original content back 30

31 The End 3