Introduction to CMOS VLSI Design Lecture 1: Introduction

Transcription

1 Introduction to CMOS VLSI Design Lecture 1: Introduction David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh

2 Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor Fast, cheap, low power transistors Today: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip 0: Introduction CMOS VLSI Design Slide 2

3 Deconstructing a Computer System 0: Introduction 3 Steven Levitan 19-Nov

4 Deconstructing a Computer System 0: Introduction 4 Steven Levitan 19-Nov

5 Deconstructing a Computer System 0: Introduction 5 Steven Levitan 19-Nov

6 Deconstructing a Computer System 0: Introduction 6 Steven Levitan 19-Nov

7 Deconstructing a Computer System 0: Introduction 7 Steven Levitan 19-Nov

8 From Chips to DIPs Single die Slicing and Dicing Wafer 0: Introduction 8 From Steven Levitan 19-Nov

9 Going Back and Zooming In Quad Core Barcelona : Introduction 9 Steven Levitan 19-Nov

10 Going Back and Zooming In M Transistors 421mm 2 0: Introduction 10 Steven Levitan 19-Nov

11 Going Back and Zooming In 1998 Pentium(II) 7.5M Transistors 118mm 2 0: Introduction 11 Steven Levitan 19-Nov

12 Going Back and Zooming In K Transistors mm 2 0: Introduction 12 Steven Levitan 19-Nov

13 Going Back and Zooming In K Transistor mm 2 0: Introduction 13 Steven Levitan 19-Nov

14 Going Back and Zooming In ECL 3-input Gate Motorola : Introduction 14 Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed Steven Levitan 19-Nov

15 Photomasks to Circuits Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed 0: IntroductionWeste & Harris CMOS VLSI Design Copyright 2005 Pearson Addison-Wesley. All rights reserved. 0: Introduction 15 Steven Levitan 19-Nov

16 The Y Abstraction Spiral Start Here End Here Gajski & Kuhn 0: Introduction 16 Steven Levitan 19-Nov

17 MOS Technology GATE 0.6 um 10um Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed 0: Introduction 17 Steven Levitan 19-Nov

18 Patterned Materials Create Circuits Silicon Crystal N type Doping P type Doping 0: IntroductionWeste & Harris CMOS VLSI Design Copyright 2005 Pearson Addison-Wesley. All rights reserved. 0: Introduction 18 Steven Levitan 19-Nov

19 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si 0: Introduction CMOS VLSI Design Slide 19

20 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) Si Si - Si Si Si + Si Si + As Si Si B - Si Si Si Si Si Si Si 0: Introduction CMOS VLSI Design Slide 20

21 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode 0: Introduction CMOS VLSI Design Slide 21

22 nmos Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Source Gate Drain Even though gate is no longer made of metal Polysilicon SiO 2 n+ n+ p bulk Si 0: Introduction CMOS VLSI Design Slide 22

23 nmos Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 0 D 0: Introduction CMOS VLSI Design Slide 23

24 nmos Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 1 D 0: Introduction CMOS VLSI Design Slide 24

25 pmos Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Source Gate Drain Polysilicon SiO 2 p+ p+ n bulk Si 0: Introduction CMOS VLSI Design Slide 25

26 Power Supply Voltage GND = 0 V In 1980 s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, 0: Introduction CMOS VLSI Design Slide 26

27 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g = 0 g = 1 d d d nmos g OFF ON s s s d d d pmos g ON OFF s s s 0: Introduction CMOS VLSI Design Slide 27

28 Transistors as Switches Input voltage on the CMOS N Switch gate controls the current through the source/drain path G D S N Switch D This provides output voltage to drive next circuit. G S Series / Parallel paths provide and and or logic functions G D S D S G 0: Introduction 28 Steven Levitan 19-Nov

29 From Switches to Boolean Functions... Use the switching functions to provide paths to Vdd or GND Vdd is the source of all Truth (Vdd = = 1) GND is the source of all Falsehood (GND == 0) P-channel 0 N-channel : Introduction 29 Steven Levitan 19-Nov

30 The Inverter True to False / False to True Converter 1/0 0/1 0: Introduction 30 Steven Levitan 19-Nov

31 CMOS Inverter A 0 Y V DD 1 A Y A Y GND 0: Introduction CMOS VLSI Design Slide 31

32 CMOS Inverter A Y A Y V DD OFF A=1 Y=0 ON GND 0: Introduction CMOS VLSI Design Slide 32

33 CMOS Inverter A Y A Y V DD ON A=0 Y=1 OFF GND 0: Introduction CMOS VLSI Design Slide 33

34 Series/Parallel Circuits => Logic +Vdd CMOS NAND (not AND) Gate A B Y Truth Table A B Y Y = A B = A + B 0: Introduction 34 Steven Levitan 19-Nov

35 CMOS NAND Gate A B Y Y A B 0: Introduction CMOS VLSI Design Slide 35

36 CMOS NAND Gate A B Y A=0 ON ON Y=1 OFF 1 1 B=0 OFF 0: Introduction CMOS VLSI Design Slide 36

37 CMOS NAND Gate A B Y A=0 OFF ON Y=1 OFF 1 1 B=1 ON 0: Introduction CMOS VLSI Design Slide 37

38 CMOS NAND Gate A B Y A=1 ON OFF Y=1 ON 1 1 B=0 OFF 0: Introduction CMOS VLSI Design Slide 38

39 CMOS NAND Gate A B Y A=1 OFF OFF Y=0 ON B=1 ON 0: Introduction CMOS VLSI Design Slide 39

40 CMOS NOR Gate A B Y A B Y 0: Introduction CMOS VLSI Design Slide 40

41 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 0: Introduction CMOS VLSI Design Slide 41

42 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 A Y B C 0: Introduction CMOS VLSI Design Slide 42

43 From Logic to Binary Math Truth tables for binary addition/subtraction etc. A B A AND Carry Sum B XOR Sum Carry Sum = A xor B Carry = A and B Are these Amino Acids? 0: Introduction 43 Steven Levitan 19-Nov

44 F = ^(AB + AC + BC) => Carry Cout C = A = B = : Introduction 44 Steven Levitan 19-Nov

45 Chip Photomask Layout 0: Introduction 45 Steven Levitan 19-Nov

46 Latches for State Cross coupled, charge storage, etc. Save logic values, change under temporal control (clocks) Set QB Reset Q DATA N+1 Inputs DATA N Outputs S R Q QB 0 0 Q QB hold Illegal Are these (folded) proteins? Latch Control (Clock) 0: Introduction 46 Steven Levitan 19-Nov

47 Finite State Machines FSM s capture processes Input Inputs, outputs, state Out = F((in), State n ) Next State & Output Calculation Output State n+1 = F(in, State n ) Like a Markov process Current State Latch S1 S5 S3 Is this a regulatory process? S2 If (state = 1) and (input = A) then state <= 4, output <= 15 0: Introduction 47 Steven Levitan 19-Nov

48 (Re) Composing 0: Introduction 48 Steven Levitan 19-Nov

49 Instruction Register Computer Micro-Architecture Basic operation on triples A <= B + C; R[2] <= R[1] op R[0] SRC1 SRC2 DEST Register File 1. Data from Register File 2. Operations done by Arithmetic and Logic Unit 3. Data returned to Register File Op CC ALU Op ={add, sub, shift, and, or, etc} CC = {zero, neg, overflow, etc} 0: Introduction 49 Steven Levitan 19-Nov

50 Instruction Set OP Code Src1 Src2 Destination Op Code Memory Address Three (four) types of instructions: 1. Move Data to / from Memory locations, I/O and temporary registers 2. Compute Logical, fixed point, floating point, string, bits 3. Program Flow Branch, Jump, Subroutines 4. Mode Control Privileged modes, interrupts, memory mapping Four addresses (explicit/implicit) Source1, Source2, Destination, Next (PC) B+C => A (and do next instruction) Instruction set and micro-architecture define the complete computing system 0: Introduction 50 Steven Levitan 19-Nov

51 von Neumann Architecture I/O CPU Control PC Accumulator IR Fetch/Execute Cycle MAR <- PC MBR <- MEM[MAR] Increment PC IR <- MBR Interpret instruction in IR MAR MBR (now called 5-stage pipeline ) Memory Done as a FSM in Control Unit Is this just like EIS.. Is this a ribosome? 0: Introduction 51 Steven Levitan 19-Nov

52 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! 0: Introduction CMOS VLSI Design Slide 52