Lecture 25. Semiconductor Memories. Issues in Memory

Transcription

1 Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1

2 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Memory Architecture: Decoders Mbits Mbits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) Nwords=>Nselectsignals Too many select signals Decoder reduces # of select signals K=log 2 N 2

3 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) Hierarchical Memory Architecture Row Address Column Address Block Address Control Circuitry Block Selector Global Amplifier/Driver I/O Global Data Bus Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings 3

4 Example:4MbitSRAM Implementing a ROM 1 VDD 0 (a) Diode ROM (b) MOS ROM 1 (c) MOS RO M 2 4

5 MOS NOR ROM Pull-up devices [0] [1] [2] [3] [0] [1] [2] [3] NOR ROM Layout s [0] [1] [2] [3] Basic cell [0] [1] [2] [3] [0] [1] [0] [1] [2] [3] [2] [3] Polysilicon Diffusion Metal1 Metal1 on top of diffusion 5

6 MOS NAND ROM [0] [1] [2] [3] Pull-up devices [0] [1] [2] [3] All word lines high by default with exception of selected row NAND ROM LAYOUT [0] [1] [2] [3] [0] [1] [2] [3] Basic cell [0] [1] [0] [1] [2] [2] [3] [3] Polysilicon Threshold Lowering Implant Diffusion Metal1 on top of diffusion 6

7 Equivalent Transient Model for MOS NOR ROM r wo rd C bi t c wo rd Equivalent Transient Model for MOS NAND ROM r bit C L r word c bi t c word 7

8 Decreasing Word Line Delay Driver Polysilicon word line Metal word line (a) Driving the word line from both sides Metal bypass K cells (b) Using a metal bypass Polysilicon word line (c) Use silicides Precharged MOS NOR ROM φpre Precharge devices [0] [1] [2] [3] [0] [1] [2] [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. 8

9 Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G t ox n + Substrate p n + S (a) Device cross-section (b) Schematic symbol Floating-Gate Transistor Programming 20 V 0V 5V 20 V 10 V 5V 5V 0V 2.5 V 5V S D S D S D Avalanche injection. Removing programming voltage leaves charge trapped. Programming results in higher V T. 9

10 FLOTOX EEPROM Source Floating gate Gate Drain I nm n + Substrate p 10 nm (a) Flotox transistor n + 10 V VGD 10 V (b) Fowler-Nordheim I-V characteristic (c) EEPROM cell during a read operation Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide n + source programming p-substrate n + drain 10

11 Cross-sections of NVM cells Flash Courtesy Intel EPROM Characteristics of State-of-the-art NVM 11

12 Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC(DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended 6-transistor CMOS SRAM Cell M2 M4 M5 Q Q M6 M1 M3 12

13 CMOS SRAM Analysis (Write) M4 M5 Q =0 Q =1 M6 M1 =1 =0 nm6 V, ( DD V Tn ) V DD k 2 8 pm4 V, ( DD V Tp ) V 2 = DD 2 8 (W/L) n,m (W/L) p,m nm5, V V 2 DD DD V 2 2 Tn k nm1, V V ( Tn ) DD V DD 2 8 = (W/L) n,m5 10 (W/L) n,m 1 CMOS SRAM Analysis (Read) M4 M5 Q =0 Q =1 M6 M1 C bit C bit k nm , V V DD DD V 2 2 Tn V 2 k 2 nm1, ( V Tn ) DD = (W/L) n,m5 10 (W/L) n,m1 (supercedes read constraint) 13

14 6T-SRAM Layout M2 M4 Q Q M1 M3 M5 M6 Resistance-load SRAM Cell R L R L M3 Q Q M4 M1 M2 Static power dissipation -- Want R L large Bit lines precharged to to address t p problem 14

15 3-Transistor DRAM Cell 1 2 W R W R M1 X M3 M2 X 1 -V T C S 2 -V T V No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V W -V Tn 3T-DRAM Layout 2 1 R M3 M2 W M1 15

16 1-Transistor DRAM Cell Write "1" Read "1" M1 C S X V T C /2 /2 sensing Write: C S is charged or discharged by asserting and. Read: Charge redistribution takes places between bit line and storage capacitance C S V = V V PRE = ( V BIT V PRE ) C S + C Voltage swing is small; typically around 250 mv. DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than. 16

17 1-T DRAM Cell Capacitor Metal word line n + poly n + poly Inversion layer induced by plate bias (a) Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon Polysilicon plate gate M1 word line (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area SEM of poly-diffusion capacitor 1T-DRAM 17

18 Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Transfer gate Isolation Storage electrode Trench Cell Stacked-capacitor Cell 18