Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995

Transcription

1 Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995 RHK.F95 1

2 Technology Trends: Microprocessor Capacity Pentium Transistors i80286 i80386 i i4004 i8080 i Year RHK.F95 2

3 Technology Trends Capacity Speed Logic 2x in 3 years 2x in 3 years dram 4x in 3 years 1.4x in 10 years disk 2x in 3 years 1.4x in 10 years Ratio to Area in Transistors per Unit Area 0 Die Size RHK.F95 3

4 nmos Transistor L drain gate gate gate oxide source W (poly) drain source (diffusion) D base Charge on the gate controls the movement of negative charge from source to drain (Vd > Vs) through the channel No charge on gate => open switch V gs > V th => conducting path Size of minimum transistor is determined by minimum width of polysilicon line, minimum feature size, RHK.F95 4

5 MOS Scaling Scaling factor L/ t/ gate poly gate source W/ (poly) drain diff depth X/ D/ gate oxide Doping N A RHK.F95 5

6 CMOS Logic Gates Inverter NAND NOR x VDD o x VDD o y VDD pmos transistor (off when charge is applied to gate) o x y V = Vdd Reservoir Water model of transistor behavior Sea RHK.F95 6

7 Ideal Scaling τ L 2 V C LW D I WV 2 LD P sw CV 2 τ P dc I V L L L L W W D D (and increase doping) V V D W W τ τ L V L 2 V 2 1 C C L W D L W D 1 I I faster less capacitance less current less power more gates 1 a P P 1 2 N N 2 power density? What if you don't scale the voltage? RHK.F95 7

8 MOS Scaling Summary Parameters Scaling Effects Length L 1/ Channel length to width ratio unchanged Width W 1/ Gate area reduced by 1/ 2 Gate Oxide D 1/ Gate dielectric thickness reduced by 1/ Junction Depth Xj 1/ Gate cap sq Cg reduced by 1/ Layer Thickness t 1/ Parasitic capacitances (ƒxj) reduced by 1/ Resistance layer thickness reduced by 1/ Subs. Doping N Resistivity ρ reduced by 1/ Sheet resistance Rs = ρ/t unchanged Time delay τ = Rs x sq Cg reduced by 1/ Inverter/gate delay reduced by 1/ Supply Voltage Vdd 1/ Current reduced by 1/ X-section of conductors reduced by 1/ 2 Current density increased by Logic levels reduced by 1/ Power diss Pd reduced by 1/ 2 Power-speed product reduced by 1/ 3 Switching Energy/circuit ƒcgvdd 2 reduced by 1/ 3 Components/unit area increased by 2 Complexity/chip increased by 2 Power diss/unit area unchanged RHK.F95 8

9 Wire and Interconnect Scaling L W Wire of length L, width W, thickness t, and resistivity ρ Resistance unscaled: Ru = ρ L / (W t) t Resistance scaled: Rsc = ρ L / W t / 2 Sheet Resistance Rs = ρ / t Rsc = Ru Original Wire Local Wire R = Rs L / W: Rs must increase by when t is scaled down by 1/ I down by 1/, IR drops remain constant Since voltage scales down by, this scales up relatively by Global Wire τsc = ( R) (C/) = R C = constant = τ Time delays of local wires do not scale! Time delays of global wires scale UP by Local communication is at a premium RHK.F95 9

10 Wire and Interconnect Scaling Summary Current density: J = I / (W t) Scaled current density: Jsc = (I / ) = J (W t / 2 ) Parameters Scaling Factor Line Resistance R Line Voltage Drop Vd 1 Normalized Line Volt drop Vd/V Current Density J Normalized contact, voltage drop Vc/V 2 RHK.F95 10

11 Transistor Timing Model I ds = charge in transit = Q = C g ( Vgs - Vth ) transit time τ time for charge to travel across channel L L L 2 v e l o c i t y µ E µ V ds C g = A = W L D D 2 mobility (cm / volt-sec ) permittivity Ids = µ e W ( Vgs Vth ) Vds LD Ids = µ e W ( Vgs Vth ) 2 LD in resistive region in saturation RHK.F95 11

12 Model of Behavior source channel drain Interface potential Vsb Vgb - Vth Vdb Cut Off: Vgs < Vth (Vgb - Vth < Vsb) Ids = 0 source channel drain source channel drain Vsb Vgb - Vth Vsb Vgb - Vth Vdb Vdb Resistive: Vgs Vth, Vds < Vgs - Vth Ids Vds Saturation: Vgs Vth, Vds Vgs - Vth Ids ( Vgs - Vth ) RHK.F95 12

13 Performance Capacity Feature size shrinks about 10% per year Switch speeds improve by 1.2x per year Switching density increases by 1.2x per year Die area increases by about 20% per year Total computing power increases by 1.73 x per year (1.2 3 ) If we can utilize every gate all the time! RHK.F95 13

14 Processor Structure bit slice Data Bus Register File Cache control line Bypass ALU Branch Unit C o n t r o l FPU RHK.F95 14

15 Fanout Reservoir C Sea Time to fill the tank: t = C / g C: capacity of the tank (capacitance) g: pipe flow (transistor strength) g FanOut 4 Inverter (FO4) RHK.F95 15

16 FO4 Timing Model Gates: Inv 1.0 Passgate 0.5 (FO2) Nand2 1.5 Mux2 1.5 Nand4 2.0 Mux4 2.0 Nor2 1.5 Nor4 3.0 TriBuff 2.0 Latch (FO16) Larger Units Adder (32 bit, not ALU) RegFile Precharge compare 1.25 / 4 bits Memory (address to data, 8Kbyte) Wires (32 bit data path in.8 µ, 1mm x 4mm) Control wire (1 mm X 2) = 10 Cg + 32 gates > 3 FO4 Global data bus = 20 Cg + GateCap + DiffCap RHK.F95 16

17 Typical Critical Paths IF RF ALU MEM WB IF RF ALU MEM WB IF RF ALU MEM WB Sparc / MIPS R3000 style pipelines ~ FO4 Alpha, R4400 style ~ 20 FO4 Where is the critical path? Register file access ALU Address -> cache Cache data -> DP Branch condition and address TLB RHK.F95 17

18 What goes in a RAM? bit (data) lines word (row) select Row Decoder row address Column Selector & I/O Circuits col address Data Spliting the address into row x col allows aspect ratio and speed to be controlled. RHK.F95 18

19 RAM Cells 6-T Static RAM cell row select Read: precharge bit and bit to Vdd row select cell pulls one line low bit bit sense amp on each column detects differential signal Dual Ported SRAM cell A row select B row select bit B bit A bit A bit B 1-T dynamic RAM cell row select bit C ~ 1 million electrons differentiate between stored 0 and 1 RHK.F95 19

20 VLSI Design Styles Full Custom Standard Cell Sea of Gates Gate Arrays Design Time / Cost Silicon Efficiency Performance NRE, Inventory Risks, Design Risks, Turn-around RHK.F95 20