Moores Law for DRAM. 2x increase in capacity every 18 months 2006: 4GB

Transcription

1 MEMORY

2 Moores Law for DRAM 2x increase in capacity every 18 months 2006: 4GB

3 Corollary to Moores Law Cost / chip ~ constant (packaging) Cost / bit = 2X reduction / 18 months Current (2008) ~ 1 micro-cent / bit

4 Total Memory Production E23 bits produced 2006: 25% growth in for flash memory for ipods

5 Types of Solid State memory Volatile memory DRAM: Dynamic Random Access Memory SDRAM: Synchronous DRAM DDR SDRAM: Double Data Rate SRAM SRAM: Static Random Access Memory Non-volatile memory FLASH: Floating gate memory FRAM: Ferroelectric memory PC-RAM: Phase change memory New things (2006 startups)

6 Memory Cell Read / Write Word Line Read / Write enabled Bit Line Write Bit Line Read

7 SRAM Cell Static Random Access Memory Word Line Turn on read / write Holds state as long as voltage on Output Negative Output 6 transistors Out M1 M2 M3 M4 1 off on >> on off 0 on off >> off on

8 Memory in Processor Intel Dual Core Processor 50% memory Processor 1 SRAM memory Processor 2 Advantages for SRAM: Fast: uses high speed logic transistors Integration: Same process as logic transistors Disadvantages: Low density (6 transistors) High power consumption due to leakage

9 DRAM Dynamic Random Access Memory Wordline (row): Enable read / write of capacitor Bitline (column): Capacitor charged = 1 Capacitor not charged = 0 Capacitor is storage element Transistor enables read / write Read: Charge transferred to read transistor Memory constantly being refreshed Read / write cycle Write: Bitline charged to Vdd or GND

10 DRAM Stacked Capacitor nfet Rough surface More area / cell Conformal oxide and electrode Capacitor leaks charge More charge (capacitance) = longer refresh time Dram requires large capacitance / area Transistor

11 DRAM Trench Capacitor nfet Deep trench for large area / cell Thermal oxide + poly Si fill Capacitor leaks charge More charge (capacitance) = longer refresh time Dram requires large capacitance / area

12 Floating Gate NVRAM Non Volatile Random Access Memory Gate Electrode isolated Minimum leakage sources Holds charge (no charge) indefinitely Electron Charge = transistor on How to charge electrode? Control Electrode isolated Charge in channel Carriers injected into floating gate How to inject charge? (a) Tunneling through oxide (b) Hot carrier injection

13 Tunneling Through Barrier Direct Tunneling Fowler-Nordheim Tunneling J ~ exp (-1/E) Thermionic Emmision J~exp(V 1/2 ) Trap Assisted Frenkel-Poole Emmision J~exp(V 1/2 ) Hot Carrier Injection High field in S/D High energy e/h pair Easier to tunnel

14 Hot Carrier Injection Gate negative Holes injected Electrons gain high kinetic energy (V D ) Bias is past pinch-off Carriers injected into p-si gap with energy > Eg/2 Substrate biased positive Electrons forced into gate

15 Charge / Clear Cycles Charge Cycle Clear Cycle Injection (fast) Tunneling (slow) Tunneling (slow) Write Cycle faster than clear cycle

16 Example of Floating Gate Flash

17 Charge Storage Flash Floating Gate Problem: Floating gate + control oxide add to device size Gate oxides must be thick for reliability Limited scaling to <90nm Store charge within gate oxide (ONO) SiN: high electron trap density = source of trapped charge

18 SiN as Charge Sponge Charge Cycle Erase Cycle SiN >> Si x N y H z Low quality SiN has trap states at specific energy (Si dangling bonds)

19 Nano-dot non-volatile memory

20 Current Flash Technology Few hundred electons / gate * 1 billion gates

21 3-D Memory Cells SiO2 anti-fuse One time programmable (OTP) Stacked memory >> no limit to memory cells / area Currently in use for games Matrix Semi. / Sandisk Inc.

22 New: Phase Change Memory Phase Change Material Word Line Crystalline GeSbGe = low resistance Bit Line Heat material with Joule Heating Rapidly cool Material freezes into: Amorphous GeSbTe = high resistance Similar technology to that for read/write CD disks Potential for multi-level integration

23 Example Phase Change Memory Cell IBM/Marconix/Toshiba Bit line Low resistance state: current through bit line High resistance state: low current through bit line

24 Ferroelectric Memory (FERAM) Symetrix, Fujitsu, Toshiba, etc Ferroelectric Crystalline Material BaSrTiO3, PbZrTiO3, etc Atom in lattice has bistable position Polarization (charge / capacitor)

25 Memresistor HP, 2008 "There should be a device that remembers how much current flowed through a device. = Memresistor What about FLASH, DRAM, PC-RAM? "It is a large amount of resistance change with a small amount of [energy]." Large memory Cell: Less than ER=1 error / 1E9 bits / s Electronic attempt times τ 0 ~1e-13 s Boltzman Statistics: ER = 1E -9 = (t/τ 0 )exp(- E/kT) E = -ln(1e-13)*ln(1e-9)* kt = 48 * 0.025eV ~ 1eV Phase change memory: DE = 100K * Cp ~

26 Memory Review Memory Type Write Speed Read Speed Density Retention SRAM Fast Fast Low (6T) Volatile DRAM Fast Fast High (1T) Volatile Floating Gate Slow Fast High (1T) 10Y Charged Gate Slow Fast High (1T) 10Y New Types Stacked MIM Read only Fast Very High >10y Phase Change Slow Slow Very High >10Y FERam Fast Fast Low 10Y