Multiplexers Decoders ROMs (LUTs) Page 1
|
|
- Egbert Bradley
- 6 years ago
- Views:
Transcription
1 Multiplexers Decoders ROMs (LUTs) Page
2 A Problem Statement Design a circuit which will select between two inputs (A and B) and pass the selected one to the output (Q). The desired circuit is called a multiplexer or MUX for short Page 2
3 Multiplexers s a b q ab s q = s a + sb a s b q Page 3
4 Multiplexer Symbols Preferred symbol a q a q b b s s Page 4
5 Data Steering a b q a b q a b q s Key idea: the select input wire selects one of the inputs and passes it out to the output. Page 5
6 Multiplexers Data Inputs { I I I 2 I 3 4-to- MUX Z A B Control Inputs Z = A B I + A BI + AB I 2 + ABI 3 Page 6
7 8 to Multiplexer I I Data Inputs I 2 I 3 I 4 8-to- MUX Z I 5 I 6 I 7 A B C Control Inputs Z = A B C I + A B CI + A BC I 2 + Page 7
8 A General MUX n Data Inputs I I I n- n: MUX Z Output s k-. s log 2 (n) Control Inputs Page 8
9 MUXes In A Microprocessor They are each 6-bits wide A 6-bit wide MUX is simply 6 -bit wide MUXes all with common s inputs Page 9
10 6-bit 3: MUX Example BusA bit bit BusB Select control lines bit BusC bit Page
11 6-bit 3: MUX Example BusA BusB BusC bit bit bit 5 Output s s They all use the same select control lines One bit from each bus goes to each MUX The result is a 6-bit bus Page
12 Implementing Logic with MUX Blocks Page 2
13 Example A B C F A= part of the truth table when A=, F= A= part of the truth table whena=, F=B+C B+C A F Page 3
14 Example 2 B A C F B= part of the truth table whenb=, F=AC B= part of the truth table whenb=, F=A AC A B F Page 4
15 Example 3 C A B F C= part of the truth table whenc=, F=AB C= part of the truth table whenc=, F=A AB A C F All 3 of these examples are the same truth table Page 5
16 Using a Bigger MUX A B C F AB= part of the truth table whenab=, F= AB= part of the truth table whenab=, F=C AB= part of the truth table whenab=, F= AB= part of the truth table whenab=, F=C C C AB F Can easily re-order truth table to use different MUX control inputs Page 6
17 Another 4: MUX Example AB F F AB This shows that a large enough MUX can directly implement a truth table Page 7
18 Implementing Logic Functions With Muxes Implement: Z = A B + BC A B I C I I 2 4-to- MUX Z I 3 for AB=, Z= A B Page 8
19 Implementing Logic Functions With Muxes Implement: Z = A B + BC A B I C I I 2 4-to- MUX Z I 3 for AB=, Z= A B Page 9
20 Implementing Logic Functions With Muxes Implement: Z = A B + BC A B I C I I 2 4-to- MUX Z C I 3 for AB=, Z=C A B Page 2
21 Implementing Logic Functions With Muxes Implement: Z = A B + BC A B I C I I 2 4-to- MUX Z C I 3 A B Page 2
22 Implementing Logic Functions With Muxes An alternate method Z = A B + BC A= B= Z = + C = I A= B= Z = + C = I 4-to- MUX Z A= B= Z = + C = I 2 A= B= Z = + C = C C I 3 A B Page 22
23 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D 3 2 X X X 8 Page 23
24 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D D I I X X I 2 I 3 8-to- MUX Z I 4 I 5 I 6 X I 7 A B C Page 24
25 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D X X D I I I 2 I 3 8-to- MUX Z I 4 I 5 I 6 X I 7 A B C Page 25
26 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D X X D I I I 2 I 3 I 4 I 5 8-to- MUX Z I 6 X I 7 A B C Page 26
27 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D X X X D D I I I 2 I 3 I 4 I 5 I 6 I 7 8-to- MUX Z A B C Page 27
28 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D B I I X X I 2 I 3 8-to- MUX Z I 4 I 5 I 6 X I 7 A C D Page 28
29 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D X X B B I I I 2 I 3 8-to- MUX Z I 4 I 5 I 6 X I 7 A C D Page 29
30 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D X X B B I I I 2 I 3 I 4 I 5 8-to- MUX Z I 6 X I 7 A C D Page 3
31 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D X X X B B I I I 2 I 3 I 4 I 5 I 6 I 7 8-to- MUX Z A C D Page 3
32 Implementing Logic Functions With Muxes An alternate method A B C D X X X Z = AC + AD + A BC + B CD B B I I I 2 I 3 I 4 I 5 I 6 I 7 8-to- MUX Z A C D Page 32
33 Implementing Logic Functions With Muxes An alternate method A C D Z = AC + AD + A BC + B CD Z = ()() + ()() + ()B() + B ()() = B Z = ()() + ()() + ()B() + B ()() = B Z = ()() + ()() + ()B() + B ()() = Z = ()() + ()() + ()B() + B ()() = B Z = ()() + ()() + ()B() + B ()() = Z = ()() + ()() + ()B() + B ()() = Z = ()() + ()() + ()B() + B ()() = Z = ()() + ()() + ()B() + B ()() = Page 33
34 Implementing Logic Functions With Muxes An alternate method A C D New Method Original Method Z = B Z = Z = B Z = B Z = Z = Z = B Z = B Z = Z = Why are they different? Z = Z = Z = Z = Z = Z = Page 34
35 Implementing Logic Functions With Muxes An alternate method A B C D X X The original method used this grouping. It was determined to be. X Z = AC + AD + A BC + B CD Page 35
36 Implementing Logic Functions With Muxes An alternate method A B C D X X The new method used this grouping. It was determined to be. X Z = AC + AD + A BC + B CD Page 36
37 Implementing Logic Functions With Muxes An alternate method A B C D X X The new method used this grouping. It was determined to be. Which is right?? X Z = AC + AD + A BC + B CD Page 37
38 Implementing Logic Functions With Muxes An alternate method A B C D X X The new method used this grouping. It was determined to be. X Which is right?? They both are!!!! Z = AC + AD + A BC + B CD Page 38
39 Implementing Logic Functions With Muxes An alternate method A B C D / X X For A= C= D= If A BC D = then input = If A BC D = then input = B They are both right!!! Page 39
40 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D B I X X I 4-to- MUX Z I 2 I 3 X A C Page 4
41 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B C D B I X X D I I 2 4-to- MUX Z I 3 X A C Page 4
42 Implementing Logic Functions With Muxes Z (A,B,C,D) = Σ m(3,5,,,2,5) + Σ d (4,8,4) A B B I C D X X B' D D I I 2 4-to- MUX Z I 3 X F = B D A C Page 42
43 Implementing Logic Functions With Muxes An alternate method A C Z = AC + AD + A BC + B CD Z = ()() + ()D + ()B() + B ()D = B Z = ()() + ()D + ()B() + B ()D = B D Z = ()() + ()D + ()B() + B ()D = D Z = ()() + ()D + ()B() + B ()D = Same as before! Page 43
44 Decoders Page 44
45 2:4 Decoder A B Q Q Q2 Q3 A B 2:4 Decode Q Q Q2 Q3 Q = A B Q = A B Q2 = AB Q3 = AB m m m2 m3 A decoder is a minterm generator Page 45
46 3:8 Decoder A B C QQQ2Q3Q4Q5Q6Q7 Q = A B C Q = A B C Q7 = ABC 3:8 Decoder m m m7 Page 46
47 Implementing Logic With Decoders 2:4 Decode F = Σ m(, 2) 2:4 Decode F = Π M(, 2) 2:4 Decode F = Σ m(, 3) Historically, some decoders have come with inverted outputs Page 47
48 Uses of Decoders Decode 3-bit op-code into a set of 8 signals op op op2 3:8 Decoder Add Sub And Xor Not Load Store Jump Page 48
49 ROM: Read-Only Memory Can read values from it Cannot write to it Address Data Address In 8 x ROM Data Out Address Data x 5 ROM Page 49
50 Read Only Memory (ROM) Each minterm of each function can be specified 3 Inputs Lines A B C ROM 8 words x 5 bits F F F 2 F 3 F 4 5 Outputs Lines A B C F F F 2 F 3 F 4 When you program a ROM, you are specifying these Page 5
51 ROM View # An addressable memory Send in address (addr n ) Receive data stored at that location (w n ) Can have multi-bit data addr2 addr addr 8 x 5 ROM w4 w3 w2 w w Page 5
52 ROM View #2 A hardware implementation of a truth table A B C F A B B C 8 x ROM F Page 52
53 ROM Two Different Views Both views are accurate Page 53
54 ROM Internal Structure n Input Lines. n:2 n decoder... Memory Array 2 n words x m bits... m Output Lines Page 54
55 ROM Memory Array V V V V V Resistors pull outputs down to GND if no row wires drive them high A B C 3:8 Decoder m =A B C m =A B C m 2 =A BC m 3 =A BC m 4 =AB C m 5 =AB C m 6 =ABC m 7 =ABC F F F 2 F 3 F 4 F = m + m4 + m7 F = m + m + m2 + m5 A diode a one-way resistor Page 55
56 ROM Technologies: Not Always Diode-Based Program Only Once Mask programmable Fusible Link Re-Programmable EPROM (ultraviolet erase) EE-PROM (electrically erase) Flash memory Beyond the scope of this class Page 56
57 Using a ROM For Logic F = AB + A BC G = A B C + C H = AB C + ABC + A B C A B C F G H Page 57
58 Using a ROM For Logic F = AB + A BC G = A B C + C H = AB C + ABC + A B C A B C F G H Page 58
59 Using a ROM For Logic F = AB + A BC G = A B C + C H = AB C + ABC + A B C A B C F G H Just fill out the truth table CAD tools usually do the rest Page 59
60 Using ROM for Combinational Logic A B C D Q ROM6X A a3 B a2 C a INIT=???? D a ROM6X is a Xilinx cell Insert it into schematics like any other primitive Set its contents by double-clicking on inserted cell in schematic. Page 6
61 Using ROM for Combinational Logic A B C D Q 8 4 D A B C D ROM6X a3 a2 a a INIT=84D Page 6
62 ROM Types in Xilinx ROM6X = 4-input LUT Specify INIT contents with 4-digit HEX value ROM32X = 5-input LUT Specify INIT contents with 8-digit HEX value Page 62
Unit 9. Multiplexers, Decoders, and Programmable Logic Devices. Unit 9 1
Unit 9 Multiplexers, ecoders, and Programmable Logic evices Unit 9 Outline Multiplexers Three state buffers ecoders Encoders Read Only Memories (ROMs) Programmable logic devices ield Programmable Gate
More informationUnit 3 Session - 9 Data-Processing Circuits
Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction
More informationSoftware Engineering 2DA4. Slides 8: Multiplexors and More
Software Engineering 2DA4 Slides 8: Multiplexors and More Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of Digital Logic
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationSlides for Lecture 19
Slides for Lecture 19 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 23 October, 2013 ENEL 353
More informationProgrammable Logic Devices
Programmable Logic Devices Mohammed Anvar P.K AP/ECE Al-Ameen Engineering College PLDs Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable
More informationMODULAR CIRCUITS CHAPTER 7
CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits BASIC LOGIC BLOCK - GATE - Logic
More informationCombinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan
Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential
More informationDigital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
More informationMenu. 7-Segment LED. Misc. 7-Segment LED MSI Components >MUX >Adders Memory Devices >D-FF, RAM, ROM Computer/Microprocessor >GCPU
Menu 7-Segment LED MSI Components >MUX >Adders Memory Devices >D-FF, RAM, ROM Computer/Microprocessor >GCPU Look into my... 1 7-Segment LED a b c h GND c g b d f a e h Show 7-segment LED in LogicWorks,
More informationSection 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic
Section 3: Combinational Logic Design Major Topics Design Procedure Multilevel circuits Design with XOR gates Adders and Subtractors Binary parallel adder Decoders Encoders Multiplexers Programmed Logic
More informationUnit 9. Multiplexers, Decoders, and Programmable Logic Devices
Unit 9. Multiplexers, Decoders, and Prograable Logic Devices Multiplexers (Data Selectors) I I I 4 to MU Z I 3 I I I 7 8 to MU Z C 4 Z I I I I 8 Z C I CI C I n Z C I n k k I k 4 CI 5 CI 3 6 CI CI 3 7 I
More informationCSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing
CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More informationChapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
More informationPart 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...
Part 1: Digital Logic and Gates Analog vs Digital waveforms An analog signal assumes a continuous range of values: v(t) ANALOG A digital signal assumes discrete (isolated, separate) values Usually there
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationSemiconductor Memory Classification
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH
More informationCh 4. Combinational Logic Technologies. IV - Combinational Logic Technologies Contemporary Logic Design 1
h 4. ombinational Logic Technologies Technologies ontemporary Logic Design 1 History - From Switches to Integrated ircuits The underlying implementation technologies for digital systems Technologies ontemporary
More informationCHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
More informationCombinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationSemiconductor Memories
Introduction Classification of Memory Devices "Combinational Logic" Read Write Memories Non Volatile RWM Read Only Memory Random Access Non-Random Access Static RAM FIFO Dynamic RAM LIFO Shift Register
More information3 Logic Function Realization with MSI Circuits
3 Logic Function Realization with MSI Circuits Half adder A half-adder is a combinational circuit with two binary inputs (augund and addend bits) and two binary outputs (sum and carry bits). It adds the
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationCombinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.
Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits
More informationKUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE
Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function
More informationLecture 22 Chapters 3 Logic Circuits Part 1
Lecture 22 Chapters 3 Logic Circuits Part 1 LC-3 Data Path Revisited How are the components Seen here implemented? 5-2 Computing Layers Problems Algorithms Language Instruction Set Architecture Microarchitecture
More informationNumber System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
More informationIntroduction to Computer Engineering. CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison
Introduction to Computer Engineering CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by
More informationBoolean Logic Continued Prof. James L. Frankel Harvard University
Boolean Logic Continued Prof. James L. Frankel Harvard University Version of 10:18 PM 5-Sep-2017 Copyright 2017, 2016 James L. Frankel. All rights reserved. D Latch D R S Clk D Clk R S X 0 ~S 0 = R 0 ~R
More informationCMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays
CMSC 33 Lecture 8 Midterm Exam returned ssign Homework 3 Circuits for ddition Digital Logic Components Programmable Logic rrays UMC, CMSC33, Richard Chang Half dder Inputs: and Outputs:
More informationLogic Design Combinational Circuits. Digital Computer Design
Logic Design Combinational Circuits Digital Computer Design Topics Combinational Logic Karnaugh Maps Combinational uilding locks Timing 2 Logic Circuit logic circuit is composed of: Inputs Outputs Functional
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationCombinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
More informationSUMMER 18 EXAMINATION Subject Name: Principles of Digital Techniques Model Answer Subject Code:
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationCSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego
CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition
More informationOverview. Programmable logic (PLAs & PALs ) Short-hand notation. Programming the wire connections
Overview Programmable logic (PLs & PLs ) Last lecture "Switching-network" logic blocks Multiplexers/selectors emultiplexers/decoders Programmable logic devices (PLs) Regular structures for 2-level logic
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More informationALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
More informationClass Website:
ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #5 Instructor: Andrew B. Kahng (lecture) Email: abk@ece.ucsd.edu Telephone: 858-822-4884 office, 858-353-0550 cell Office:
More informationLogic. Combinational. inputs. outputs. the result. system can
Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction
More informationDHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number
More informationHw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today
EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS141 2 1 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 Frequency
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Decoders and Encoders CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationXI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.
2017-18 XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL HALF ADDER 1. The circuit that performs addition within the Arithmetic and Logic Unit of the CPU are called adders. 2. A unit that adds two
More informationDigital System Design Combinational Logic. Assoc. Prof. Pradondet Nilagupta
Digital System Design Combinational Logic Assoc. Prof. Pradondet Nilagupta pom@ku.ac.th Acknowledgement This lecture note is modified from Engin112: Digital Design by Prof. Maciej Ciesielski, Prof. Tilman
More information( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationMagnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
More informationSlide Set 6. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 6 for ENEL 353 Fall 2017 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2017 SN s ENEL 353 Fall 2017 Slide Set 6 slide
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationECE 2300 Digital Logic & Computer Organization
ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5: Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed
More informationCombinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.
Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Combinational Circuits
More informationCMP 334: Seventh Class
CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative
More informationDigital Circuits. 1. Inputs & Outputs are quantized at two levels. 2. Binary arithmetic, only digits are 0 & 1. Position indicates power of 2.
Digital Circuits 1. Inputs & Outputs are quantized at two levels. 2. inary arithmetic, only digits are 0 & 1. Position indicates power of 2. 11001 = 2 4 + 2 3 + 0 + 0 +2 0 16 + 8 + 0 + 0 + 1 = 25 Digital
More informationCOSC3330 Computer Architecture Lecture 2. Combinational Logic
COSC333 Computer rchitecture Lecture 2. Combinational Logic Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston Today Combinational Logic oolean lgebra Mux, DeMux, Decoder
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
More informationChapter 3 Combinational Logic Design
Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 1- Implementation Technology and Logic Design Overview Part 1-Implementation Technology and Logic Design Design Concepts
More informationCS/COE0447: Computer Organization and Assembly Language
CS/COE0447: Computer Organization and Assembly Language Logic Design Introduction (Brief?) Appendix B: The Basics of Logic Design Dept. of Computer Science Logic design? Digital hardware is implemented
More informationSemiconductor Memories
!"#"$%&'()$*#+%$*,' -"+./"$0 1'!*0"#)'2*+03*.$"4* Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 !"#$%&'()*&'*+&, Memory Classification Memory Architectures
More informationDigital Integrated Circuits Lecture 14: CAMs, ROMs, and PLAs
Digital Integrated Circuits Lecture 4: CAMs, ROMs, and PLAs Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec4 cwliu@twins.ee.nctu.edu.tw Outline
More informationSAU1A FUNDAMENTALS OF DIGITAL COMPUTERS
SAU1A FUNDAMENTALS OF DIGITAL COMPUTERS Unit : I - V Unit : I Overview Fundamentals of Computers Characteristics of Computers Computer Language Operating Systems Generation of Computers 2 Definition of
More informationEGC221: Digital Logic Lab
Division of Engineering Programs EGC221: Digital Logic Lab Experiment #1 Basic Logic Gate Simulation Student s Name: Student s Name: Reg. no.: Reg. no.: Semester: Fall 2016 Date: 07 September 2016 Assessment:
More informationIntroduction to Karnaugh Maps
Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationChapter 3 Combinational Logic Design
Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 2 Combinational Logic Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
More informationIntroduction to Computer Engineering. CS/ECE 252, Spring 2017 Rahul Nayar Computer Sciences Department University of Wisconsin Madison
Introduction to Computer Engineering CS/ECE 252, Spring 2017 Rahul Nayar Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by
More informationCOMP2611: Computer Organization. Introduction to Digital Logic
1 OMP2611: omputer Organization ombinational Logic OMP2611 Fall 2015 asics of Logic ircuits 2 its are the basis for binary number representation in digital computers ombining bits into patterns following
More information3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value
EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal 35.77 33.23.875 29.99 27 9 64 Hexadecimal B.3 D.FD B.4C 2. Calculate the following
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
More informationChapter 3 Ctd: Combinational Functions and Circuits
Chapter 3 Ctd: Combinational Functions and Circuits 1 Value Fixing, Transferring, and Inverting Four different functions are possible as a function of single Boolean variable Transferring Inverting Value
More informationVidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B
. (a). (b). (c) S.E. Sem. III [EXTC] igital Electronics Prelim Question Paper Solution ABC ABC ABC ABC ABC ABC ABC ABC = B LHS = ABC ABC ABC ABC ABC ABC ABC ABC But ( ) = = ABC( ) ABC( ) ABC( ) ABC( )
More informationUNIT II COMBINATIONAL CIRCUITS:
UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates
More informationReg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering
Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common
More informationComputer Science. 19. Combinational Circuits. Computer Science COMPUTER SCIENCE. Section 6.1.
COMPUTER SCIENCE S E D G E W I C K / W A Y N E PA R T I I : A L G O R I T H M S, M A C H I N E S, a n d T H E O R Y Computer Science Computer Science An Interdisciplinary Approach Section 6.1 ROBERT SEDGEWICK
More informationECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational
More informationCSEE 3827: Fundamentals of Computer Systems. Combinational Circuits
CSEE 3827: Fundamentals of Computer Systems Combinational Circuits Outline (M&K 3., 3.3, 3.6-3.9, 4.-4.2, 4.5, 9.4) Combinational Circuit Design Standard combinational circuits enabler decoder encoder
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 5 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationThe Digital Logic Level
The Digital Logic Level Wolfgang Schreiner Research Institute for Symbolic Computation (RISC-Linz) Johannes Kepler University Wolfgang.Schreiner@risc.uni-linz.ac.at http://www.risc.uni-linz.ac.at/people/schreine
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationDesign of Combinational Logic
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK 3. Design of Combinational Logic By Prof. Anand N. Gharu (Assistant Professor) PVGCOE Computer Dept.. 30 th June 2017 CONTENTS :- 1. Code Converter
More informationChapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability. Memory
SRAM Design Chapter Overview Classification Architectures The Core Periphery Reliability Semiconductor Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna Today! Memory " Classification " ROM Memories " RAM Memory
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor
More informationChapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms
Chapter 2 (Lect 2) Canonical and Standard Forms Sum of Minterms Product of Maxterms Standard Form Sum of products Product of sums Other Logic Operators Logic Gates Basic and Multiple Inputs Positive and
More informationCSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April
CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April Objective - Get familiar with the Xilinx ISE webpack tool - Learn how to design basic combinational digital components -
More informationCSE370 HW3 Solutions (Winter 2010)
CSE370 HW3 Solutions (Winter 2010) 1. CL2e, 4.9 We are asked to implement the function f(a,,c,,e) = A + C + + + CE using the smallest possible multiplexer. We can t use any extra gates or the complement
More informationDE58/DC58 LOGIC DESIGN DEC 2014
Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5
More informationKarnaugh Maps (K-Maps)
Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC
More informationChapter 1: Logic systems
Chapter 1: Logic systems 1: Logic gates Learning Objectives: At the end of this topic you should be able to: identify the symbols and truth tables for the following logic gates: NOT AND NAND OR NOR XOR
More information