ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks


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1 ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks
2 Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational Logic Building Blocks Multiplexers Decoders, Demultiplexers Encoders, Priority Encoders Arithmetic circuits ROM. Implementing combinational logic using ROM. Tristate buffers. 2
3 Textbook References Combinational Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2 nd or 3 rd Edition Chapter 2 Introduction to Logic Circuits ( only) Chapter 6 CombinationalCircuit Building Blocks ( only) OR your undergraduate digital logic textbook (chapters on combinational logic) 3
4 Basic Logic Review some slides modified from: S. Dandamudi, Fundamentals of Computer Organization and Design 4
5 Basic Logic Gates (2input versions) 5
6 Basic Logic Gates Generalized Simple logic gates AND à if one or more inputs is OR à if one or more inputs is NAND = AND + NOT if one or more inputs is NOR = OR + NOT if one or more input is XOR à if an odd number of inputs is XNOR à if an even number of inputs is NAND and NOR gates require fewer transistors than AND and OR in standard CMOS Functionality can be expressed by a truth table A truth table lists output for each possible input combination 6
7 Number of Functions Number of functions With N logical variables, we can define 2 2N functions Some of them are useful AND, NAND, NOR, XOR, Some are not useful: Output is always Output is always Number of functions definition is useful in proving completeness property 7
8 Complete Set of Gates Complete sets A set of gates is complete if we can implement any logic function using only the type of gates in the set Some example complete sets {AND, OR, NOT} {AND, NOT} {OR, NOT} {NAND} {NOR} Minimal complete set A complete set with no redundant elements. Not a minimal complete set 8
9 NAND as a Complete Set Proving NAND gate is universal 9
10 Logic Functions Logic functions can be expressed in several ways: Truth table Logical expressions Graphical schematic form HDL code Example: Majority function Output is one whenever majority of inputs is We use 3input majority function
11 Alternative Representations of Logic Function Truth table A B C F HDL code: Logical expression form F = A B + B C + A C Graphical schematic form F <= (A AND B) OR (B AND C) OR (A AND C) ;
12 Boolean Algebra Boolean identities Name AND version OR version Identity x. = x x + = x Complement x. x = x + x = Commutative x. y = y. x x + y = y + x Distribution x. (y+z) = xy+xz x + (y. z) = (x+y) (x+z) Idempotent x. x = x x + x = x Null x. = x + = 2
13 Boolean Algebra (cont d) Boolean identities (cont d) Name AND version OR version Involution x = (x )  Absorption x. (x+y) = x x + (x. y) = x Associative x. (y. z) = (x. y). z x + (y + z) = (x + y) + z de Morgan (x. y) = x + y (x + y) = x. y (de Morgan s law in particular is very useful) 3
14 Alternative symbols for NAND and NOR 4
15 Majority Function Using Other Gates Using NAND gates Get an equivalent expression A B + C D = (A B + C D) Using de Morgan s law A B + C D = ( (A B). (C D) ) Can be generalized Example: Majority function A B + B C + AC = ((A B). (B C). (AC) ) 5
16 Majority Function Using Other Gates (cont'd) Majority function 6
17 Combinational Logic Building Blocks Some slides modified from: S. Dandamudi, Fundamentals of Computer Organization and Design S. Brown and Z. Vranesic, "Fundamentals of Digital Logic" 7
18 Multiplexers log 2 n selection inputs n inputs output multiplexer n binary inputs (binary input = bit input) log 2 n binary selection inputs binary output Function: one of n inputs is placed onto output Called nto multiplexer 8
19 2to Multiplexer s s f w w f w w (a) Graphical symbol (b) Truth table w w s f s w w f (c) Sumofproducts circuit (d) Circuit with transmission gates Source: Brown and Vranesic 9
20 4to Multiplexer s s s s f w w w 2 w 3 f w w w 2 w 3 (a) Graphic symbol (b) Truth table s s w w f w 2 w 3 Source: Brown and Vranesic (c) Circuit 2
21 Multibit 4to Multiplexer s s s s f w w w 2 w f w w w 2 w 3 (a) Graphic symbol (b) Truth table When drawing schematics, can draw multibit multiplexers Example: 8bit 4to multiplexer 4 inputs (each 8 bits) output (8 bits) 2 selection bits Can also have multibit 2to muxes, 6to muxes, etc. 2
22 8bit 4to Multiplexer s s w (7) w (7) w 2 (7) w 3 (7) f(7) s s w w w 2 w 3 8 f = 8 s s w (6) w (6) w 2 (6) w 3 (6) f(6) An 8bit 4to multiplexer is composed of eight [bit] 4to multiplexers s s w () w () w 2 () w 3 () f() 22
23 Decoders n inputs w y 2 n w n 2 n outputs Enable En y Decoder n binary inputs 2 n binary outputs Function: decode encoded information If enable=, one output is asserted high, the other outputs are asserted low If enable=, all outputs asserted low Often, enable pin is not needed (i.e. the decoder is always enabled) Called nto2 n decoder Can consider n binary inputs as a single nbit input Can consider 2 n binary outputs as a single 2 n bit output Decoders are often used for RAM/ROM addressing 23
24 2to4 Decoder En w w y 3 y 2 y y   w En y 3 w y 2 y y (a) Truth table (b) Graphical symbol w y w y y 2 y 3 Source: Brown and Vranesic En (c) Logic circuit 24
25 Demultiplexers log 2 n selection inputs input n outputs Demultiplexer binary input n binary outputs log 2 n binary selection inputs Function: places input onto one of n outputs, with the remaining outputs asserted low Called ton demultiplexer Closely related to decoder Can build ton demultiplexer from log 2 nton decoder by using the decoder's enable signal as the demultiplexer's input signal, and using decoder's input signals as the demultiplexer's selection input signals. 25
26 to4 Demultiplexer 26
27 Encoders 2 n inputs w 2 n w y y n n outputs Encoder 2 n binary inputs n binary outputs Function: encodes information into an nbit code Called 2 n ton encoder Can consider 2 n binary inputs as a single 2 n bit input Can consider n binary output as a single nbit output Encoders only work when exactly one binary input is equal to 27
28 4to2 Encoder w 3 w 2 w w y y (a) Truth table w w y w 2 w 3 y (b) Circuit 28
29 Priority Encoders 2 n inputs w 2 n w y n n outputs y z "valid" output Priority Encoder 2 n binary inputs n binary outputs binary "valid" output Function: encodes information into an nbit code based on priority of inputs Called 2 n ton priority encoder Priority encoder allows for multiple inputs to have a value of '', as it encodes the input with the highest priority (MSB = highest priority, LSB = lowest priority) "valid" output indicates when priority encoder output is valid Priority encoder is more common than an encoder 29
30 3 4to2 MSB Priority Encoder  w y  y z w   w 2  w 3
31 SingleBit Adders Halfadder Adds two binary (i.e. bit) inputs A and B Produces a sum and carryout Problem: Cannot use it alone to build larger adders Fulladder Adds three binary (i.e. bit) inputs A, B, and carryin Like halfadder, produces a sum and carryout Allows building Mbit adders (M > ) Simple technique Connect C out of one adder to C in of the next These are called ripplecarry adders 3
32 HalfAdder c x 2 s HA x + y = ( c s ) 2 y x y c s 32
33 33 FullAdder x y c out s FA x + y + c in = ( c out s ) 2 2 x y c out s c in c in x y c in s c out
34 6bit Unsigned Adder 6 6 Cout X + S Y Cin 6 34
35 MultiBit RippleCarry Adder A 6bit ripplecarry adder is composed of 6 (bit) full adders Inputs: 6bit A, 6bit B, bit carry in (set to zero in the figure below) Outputs: 6bit sum S, bit carry out Other multibit adder structures can be studied in ECE 645 Computer Arithmetic Called a ripplecarry adder because carry ripples from one fulladder to the next. Critical path is 6 fulladders. 35
36 Comparator Used two compare two Mbit numbers and produce a flag (M >) Inputs: Mbit input A, Mbit input B Output: bit output flag indicates condition is met indicates condition is not met Can compare: >, >=, <, <=, =, etc. A B M M A > B? if A > B if A <= B 36
37 Example: 4bit comparator (A = B) A B 4 4 A = B? if A = B if A!= B 37
38 4x4bit Unsigned Multiplier 4 4 a * c b U 8 38
39 4x4bit Signed Multiplier 4 4 a * c b S 8 39
40 Unsigned vs. Signed Multiplication Unsigned Signed 5  x x 5 x x
41 Quotient and remainder Given integers a and n, n>! q, r Z such that a = q n + r and r < n q quotient r remainder (of a divided by n) q = a n = a div n r = a  q n = a = a mod n a n n = 4
42 Rules of addition, subtraction and multiplication modulo n a + b mod n = ((a mod n) + (b mod n)) mod n a  b mod n = ((a mod n)  (b mod n)) mod n a b mod n = ((a mod n) (b mod n)) mod n 42
43 Logical Shift Right 4 A >> C 4 L A(3) A(2) A() A() A(3) A(2) A() A C 43
44 Arithmetic Shift Right 4 A >> C 4 A A(3) A(2) A() A() A C A(3) A(3) A(2) A() 44
45 Fixed Rotation 4 A <<< C 4 A(3) A(2) A() A() A(2) A() A() A(3) A C 45
46 8bit Variable Rotator Left A 8 3 B A <<< B C 8 46
47 Read Only Memory (ROM) m ADDR ROM DOUT n 47
48 Implementing Arbitrary Combinational Logic Using ROM X 5 X 4 X 3 X 2 X Y ADDR DOUT 5 ROM 48
49 Tristate Buffer e x f e = (a) A tristate buffer x f e x f Z Z x e = (b) Equivalent circuit f (c) Truth table 49
50 Four types of Tristate Buffers e e x f x f (a) (b) e e x f x f (c) (d) 5
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