Unit 3 Session - 9 Data-Processing Circuits

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1 Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction Data-processing circuits are logic circuits that process binary data. Such circuits may be multiplexers, demultiplexers, encoder, decoder, EX-OR gates. First we consider multiplexers. Multiplexer Multiplex means many into one. In digital computer networks, multiplexing is a method by which multiple digital data streams are combined into one signal over a shared medium. A digital circuit that performs the multiplexing of digital signals is called a multiplexer (or MUX in short). Multiplexer is a combinational logic circuit that can select one of many inputs. Multiplexer is also called a data selector. A simple 2-to-1 multiplexer block diagram and the switch equivalent circuit are as shown: It has two inputs but only one output. By suitable control input or select input (sel) we can steer any input to the output. Page 1

2 The general multiplexer block diagram is as shown below: Design of 4-to-1 Multiplexer The 4-to-1 multiplexer has four data inputs. To steer the four data inputs to the output we need two control inputs. The block diagram is as shown below: The truth table describing the behavior of the 4-to-1 multiplexer is as shown below: Control Inputs Output A B Y 0 0 D0 0 1 D1 1 0 D2 1 1 D3 Page 2

3 From the truth table we obtain the logic equation Y = A B D 0 + A BD 1 + AB D 2 + ABD 3 The equation cannot be further simplified. The logic circuit realization is as shown below: Y = A B D 0 + A BD 1 + AB D 2 + ABD 3 The The is a 16-to-1 TTL multiplexer. It has active low output. It has a STROBE, an input signal that disables or enables the multiplexer.. If STROBE = 0, MUX is enabled and if STROBE = 1, MUX is disabled. The block diagram is as shown below: The The is an 8-to-1 TTL multiplexer. It has complementary outputs. Page 3

4 The block diagram is as shown below: The The is a dual 4-to-1 TTL multiplexer. It has non-inverting outputs. It has separate enable for each multiplexer and common select lines. The The is a quad 2-to-1 TTL multiplexer IC. The block diagram is as shown below: Page 4

5 Multiplexer Applications Multiplexer s important application is in sharing the circuits, ports, devices and resources. Multiplexers can be used in design of combinational logic circuits. Nibble Multiplexer Nibble Multiplexer is used when we want to select one of two input nibbles. Consider the two input nibbles, A3A2A1A0 and B 3 B 2 B 1 B 0. The IC is used to realize the nibble multiplexer as shown below: The control signal SELECT determines which nibble is transmitted to output. STROBE input is made 0. When SELECT is low, the left nibble is steered to the output. We have, Y 3 Y 2 Y 1 Y 0 = A 3 A 2 A 1 A 0 When SELECT is high, the right nibble is steered to the output. We have, Y 3 Y 2 Y 1 Y 0 = B 3 B 2 B 1 B 0 Multiplexer Logic We can use multiplexer to realize a given Boolean equation. Multiplexer is called universal logic circuit because a 2 n -to-1 multiplexer can be used to design solution for any n-variable truth table. Example 1: Realize Y = A B + B C + ABC using an 8-to-1 multiplexer Solution: First we express Y in canonical SOP form Page 5

6 Y = A B + B C + ABC = A B B C + ABC = A B.(C + C) + (A + A).B C + ABC = A BC + A BC + A B C + AB C + ABC = Σ m (2, 3, 0, 4, 7) = Σ m (0, 2, 3, 4, 7) Consider the 8-to-1 multiplexer truth table as shown below: A B C Y D D D D D D D D 7 From the truth table we have, Y = A B C D 0 + A B CD 1 + A BC D 2 + A BCD 3 + AB C D 4 + AB CD 5 + ABC D 6 + ABCD 7 Y = m o D 0 + m 1 D 1 + m 2 D 2 + m 3 D 3 + m 4 D 4 + m 5 D 5 + m 6 D 6 + m 7 D 7 The given equation is Y = f(a, B, C) = Σ m (0, 2, 3, 4, 7). The variables A, B, & C are used as select inputs. Comparing multiplexer output expression with the given logic equation in canonical SOP form we find by substituting D 0 = D 2 = D 3 = D 4 = D 7 = 1 and D 1 = D 5 = D 6 = 0 we have the realization as shown. Page 6

7 The truth table for the given logic equation is shown below: A B C Y Example 2: Realize Y = A B + B C + ABC using 4-to-1 multiplexer. Solution: We consider variables A and B as selector inputs in 4-to-1 multiplexer and variable C in given as data input. Given logic equation Y = A B + B C + ABC in canonical form is Y= Σ m (0, 2, 3, 4, 7). The truth table is as shown. Page 7

8 A B C Y Similar to procedure adopted in entered variable map, output Y is written in terms of variable C. A B C Y Y C 1 C C Comparing with equation of 4-to-1 multiplexer we see D 0 = C D 1 = 1 D 2 = C D 3 = C generate the given logic function. Page 8

9 The given logic equation is realized using the 4-to-1 multiplexer as shown below: A B Y 0 0 C C 1 1 C Example 3: Realize Y = Σ m(0, 2, 3, 4,5, 8, 9, 10, 11, 12, 13, 15) using 8-to-1 multiplexer. Solution: The truth table for the given expression is as shown below: Page 9

10 The logic expression is realized using 8-to-1 multiplexer as shown below: Multiplexer Trees A number of m-to-1 multiplexers can be arranged in tree topology to obtain a bigger n-to-1 multiplexer (n > m). Example 1: Design a 4-to-1 multiplexer using 2-to-1 multiplexers. Solution: The 2-to-1 multiplexer truth table is as shown: A B Y 0 0 D D D D 3 Two units of 2-to-1 multiplexers are used together to realize 4 inputs, and another unit of 2-to-1 multiplexer is used to steer the inputs to a single output. The multiplexer tree is realized as shown: Page 10

11 Example 2: Design a 32-to-1 multiplexer using two 16-to-1 multiplexers and one 2-to-1 multiplexer. Solution: Questions 1. What is a multiplexer? Design 4-to-1 multiplexer and implement using gates. 2. Implement the given Boolean function by using 8:1 multiplexer. f(a, B, C, D) = m(0, 1, 3, 5, 7, 11, 12, 13, 14) Page 11

12 3. Realize the Boolean expression f(w, x, y, z) = m(4, 6, 7, 8, 10, 12, 15) using a 4 to 1 line multiplexer and external gates. 4. Write the truth table of a 4-bit Binary to Gray code converter and realize the same using four ICs (8-to-1 multiplexer). 5. Show how two 1-to-16 demultiplexers can be connected to get a 1-to-32 demultiplexer. 6. Design a 32-to-1 multiplexer using two 16-to-1 multiplexer and one 2-to-1 multiplexer. Page 12

Design of Combinational Logic

Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK 3. Design of Combinational Logic By Prof. Anand N. Gharu (Assistant Professor) PVGCOE Computer Dept.. 30 th June 2017 CONTENTS :- 1. Code Converter