Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

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1 Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw

2 Combinational Circuits Analysis Procedure Design Procedure Binary Adder-Subtractor Decimal Adder Binary Multiplier Decoders Encoders Multiplexers HDL Description Outlines DCD-04-2

3 Introduction Logic circuits for digital systems may be either combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. DCD-04-3

4 Combinational Circuits A combinational circuits 2 n possible combinations of input values n input variables Combinational Logic Circuit m output variables Specific functions Adders, subtractors, comparators, decoders, encoders, and multiplexers MSI circuits or standard cells DCD-04-4

5 Analysis Procedure Step 1: Label all gate outputs that are a function of input variables with arbitrary symbols but with meaningful names. Determine the Boolean functions for each gate output. Step 2: Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates. Step 3: Repeat the process outlined in step 2 until the outputs of the circuit are obtained. Step 4: By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables. DCD-04-5

6 Analysis Procedure Example A straight-forward procedure DCD-04-6

7 Analysis Procedure Example Step 1: F 2 = AB+AC+BC T 1 = A+B+C T 2 = ABC Step 2: T 3 = F 2 'T 1 Step 3: F 1 = T 3 +T 2 Step 4: F 1 = T 3 +T 2 = F 2 'T 1 +ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C')(B'+C')(A+B+C)+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B'C+AB'C'+ABC DCD-04-7

8 Truth Table DCD-04-8

9 Design Procedure The design procedure of combinational circuits Step 1: State the problem (system spec.) Step 2: From the specifications of the circuits, determine the required number of inputs and outputs and assign a symbol to each. Step 3: Derive the truth table that defined the required relationship between inputs and outputs Step 4: Obtain the simplified Boolean functions for each output as a function of the input variables. Step 5: Draw the logic diagram and verify the correctness of the design (manually or by simulation). DCD-04-9

10 Design Method and Constraint Functional description Boolean function HDL (Hardware description language) Verilog HDL VHDL Schematic entry Logic constraint number of gates number of inputs to a gate propagation delay number of interconnections limitations of the driving capabilities DCD-04-10

11 BCD to Excess-3 Code Conversion Digital Circuit Design DCD-04-11

12 BCD to Excess-3 Code Conversion Digital Circuit Design DCD-04-12

13 BCD to Excess-3 Code Conversion Digital Circuit Design Simplified functions z = D' y = CD +C'D' x = B'C + B'D+BC'D' w = A+BC+BD Efficient implementation z = D' y = CD +C'D'= CD + (C+D) x = B'C + B'D+BC'D = B'(C+D) +B(C+D)' w = A+BC+BD= A+ B(C+D) DCD-04-13

14 Logic Diagram for BCD to Excess-3 Code Converter Digital Circuit Design DCD-04-14

15 1-Bit Half Adder Half adder = 0 ; = 1 ; = 1 ; = (10) 2 two input variables: x, y two output variables: C (carry), S (sum) truth table S = x'y+xy'=x y= (x+y)(x'+y') C = xy= (x'+y')' S' = xy+x'y' S = (C+x'y')' DCD-04-15

16 Logic Diagram of 1-Bit Half Adder Digital Circuit Design DCD-04-16

17 Full-Adder The arithmetic sum of three input bits three input bits x, y: two significant bits z: the carry bit from the previous lower significant bit Two output bits: C, S 1-Bit Full Adder Sum Carry DCD-04-17

18 Logic Diagram of 1-Bit Full Adder Digital Circuit Design DCD-04-18

19 Logic Diagram of 1-Bit Full Adder Digital Circuit Design S = x'y'z+x'yz'+ xy'z'+xyz = x (y z) +x(y z) = x y z C = xy + xz + yz = xy + xyz + xy z + xyz + x yz = xy + z (x y + xy) = xy + z (x y) DCD-04-19

20 4-Bit Full Adder Binary adder DCD-04-20

21 Carry Lookahead Adder (1/7) Given Stage i from a Full Adder, we know that there will be a carry generated when A i = B i = "1", whether or not there is a carry-in. Alternately, there will be a carry propagated if the half-sum is "1" and a carry-in, C i occurs. These two signal conditions are called generate, denoted as G i, and propagate, denoted as P i respectively and are identified in the circuit. G i C i+1 A i B i P i C i S i Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-21

22 Carry Lookahead Adder (2/7) In the ripple carry adder: G i, P i, and S i are local function to each cell of the adder C i is also local function for each cell In the carry lookahead adder, in order to reduce the length of the carry chain, C i is changed to a more global function spanning multiple cells Defining the equations for the Full Adder in term of the P i and G i : P i = A B G = Ai Bi S = G + P i i i i = Pi Ci Ci+ 1 i i C i Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-22

23 Carry Lookahead Adder (3/7) C i+1 can be removed from the cells and used to derive a set of carry equations spanning multiple cells. Beginning at the cell 0 with carry in C 0 : C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 (G 1 + P 1 G 0 + P 1 P 0 C 0 ) = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-23

24 Carry Lookahead Adder (4/7) DCD-04-24

25 Carry Lookahead Adder (5/7) DCD-04-25

26 Carry Lookahead Adder (6/7) CLA GEN Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-26

27 Carry Lookahead Adder (7/7) DCD This lookahead scheme could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible. Instead, the concept is extended another level by considering group generate (G 0-3 ) and group propagate (P 0-3 ) functions: G Using these two equations: P = = G P 3 3 P + 2 P P 1 3 P G C4 = G0-3 + P0-3 C0 P Thus, it is possible to have five 4-bit carry lookahead generator circuit to speed up 16-bit addition (see next slide). 3 P 2 G 1 + P 3 P 2 P 1 G C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. 0

28 16-bit 2-level Carry Lookahead Adder c 11 c 9 c 8 c 4 c 3 G 14 P 14 G 12 P 12 G 15 P 15 G 13 P 13 G 10 P 10 G 11 P 11 G 9 P 9 G 8 P 8 G 7 P 7 G 6 P 6 G 4 P 4 G 5 P 5 G 3 P 3 G 2 P 2 G 1 P 1 G 0 P 0 CLA GEN c 12 CLA GEN c 8 CLA GEN c 4 CLA GEN c 0 G P G 8-11 P 8-11 G 4-7 P 4-7 G 0-3 P 0-3 CLA GEN G 0-15 P

29 4-Bit Adder/Subtractor A-B = A+(2 s complement of B) 4-bit adder-subtractor M=0, A+B; M=1, A+B +1 DCD-04-29

30 Overflow Discussion Overflow The storage is limited. Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V = 0, no overflow; V = 1, overflow Example: DCD-04-30

31 BCD Adder Add two decimal digits in BCD together with an input carry from a previous stage 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches Since each input digit does not exceed 9, the output sum cannot be grater than =19, where 1 denotes an input carry. A truth table with 19 entries Use two 4-bit binary full adders Modifications are needed if the binary sum > 9 C = 1 K = 1 Z 8 Z 4 = 1 Z 8 Z 2 = 1 modification: +6 C = K +Z 8 Z 4 + Z 8 Z 2 DCD-04-31

32 Truth Table of BCD Adder DCD-04-32

33 Logic Diagram of BCD Adder BCD BCD BCD Output DCD-04-33

34 Binary Multiplier DCD-04-34

35 4-Bit by 3-Bit Binary Multiplier DCD-04-35

36 Magnitude Comparator The comparison of two numbers outputs: A>B, A=B, A<B Design Approaches the truth table 2 2n entries - too cumbersome for large n use inherent regularity of the problem reduce design efforts reduce human errors Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 0 =B 0 equality: x i = A i B i +A i 'B i ' (A=B) = x 3 x 2 x 1 x 0 (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A<B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Implementation x i = (A i B i '+A i 'B i )' DCD-04-36

37 Four-Bit Magnitude Comparator DCD-04-37

38 An n-to-m decoder Decoder a binary code of n bits = 2 n distinct information n input variables; up to 2 n output lines only one output can be active (high) at any time DCD-04-38

39 Three-to-Eight Line Decoder x y z DCD-04-39

40 Demultiplexers Decoder with Enable /Demultiplexer a decoder with an enable input receive information on a single line and transmits it on one of 2 n possible output lines Digital Circuit Design 0 Two-to-four-line decoder with enable input DCD-04-40

41 Decoder with Enable /Demultiplexer Digital Circuit Design DCD-04-41

42 Expansion 4x16 Decoder two 3-to-8 decoder: a 4-to-16 decoder 4 16 decoder constructed with two 3 8 decoders DCD-04-42

43 Combinational Logic Implementation Digital Circuit Design Each output = a minterm Use a decoder and an external OR gate to implement any Boolean function of n input variables A full-adder S(x,y,z)=S(1,2,4,7) C(x,y,z)= S(3,5,6,7) DCD-04-43

44 Encoder z = D + D + D + D y = D + D + D + D x = D + D + D + D Lan-Da 7 Van The encoder can be implemented with three OR gates. DCD-04-44

45 Encoder An implementation x=d 4 +D 5 +D 6 +D 7 y=d 2 +D 3 +D 6 +D 7 z=d 1 +D 3 +D 5 +D 7 limitations illegal input: e.g. D 3 =D 6 =1 the output = 111 (¹3 and ¹6) DCD-04-45

46 Priority Encoder Resolve the ambiguity of illegal inputs Only one of the input is encoded LSB MSB D 3 has the highest priority D 0 has the lowest priority X: don't-care conditions V: valid output indicator DCD-04-46

47 Priority Encoder 1 DCD-04-47

48 Priority Encoder x = D + D 2 3 y = D + D D V = D + D + D + D DCD-04-48

49 Multiplexer Select binary information from one of many input lines and direct it to a single output line 2 n input lines, n selection lines and one output line E.g.: 2-to-1-line multiplexer Two-to-one-line multiplexer DCD-04-49

50 4-to-1-Line Multiplexer DCD-04-50

51 Boolean Function Implementation Using MUX MUX: a decoder + an OR gate Digital Circuit Design 2 n -to-1 MUX can implement any Boolean function of n input variable. Procedure: assign an ordering sequence of the input variable the rightmost variable (D) will be used for the input lines assign the remaining n-1 variables to the selection lines w.r.t. their corresponding sequence construct the truth table consider a pair of consecutive minterms starting from m 0 determine the input lines DCD-04-51

52 Boolean Function Implementation Using MUX Example: Given F(x,y,z) = S(1,2,6,7) Digital Circuit Design DCD-04-52

53 Boolean Function Implementation Using MUX Digital Circuit Design Example: Given F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15) DCD-04-53

54 Three-State Gate A multiplexer can be constructed with three-state gates. Output state: 0, 1, and high-impedance (open ckts) DCD-04-54

55 Four-to-One-Line Multiplexer DCD-04-55

56 4-12 HDL Models of Combinational Circuits Modeling Styles: Gate-level modeling using instantiations of predefined and user-defined primitive gates. Dataflow modeling using continuous assignment statements with the keyword assign. Behavioral modeling using procedural assignment statements with the keyword always. Digital Circuit Design 56

57 57

58 Gate-level Modeling Digital Circuit Design The four-valued logic truth tables for the and, or, xor, and not primitives 58

59 Gate-level Modeling Digital Circuit Design Example: output [0: 3] D; wire [7: 0] SUM; 1. The first statement declares an output vector D with four bits, 0 through The second declares a wire vector SUM with eight bits numbered 7 through 0. 59

60 HDL Example 4-1 Digital Circuit Design Two-to-Four-line decoder 60

61 HDL Example 4-2 (1/2) Four-bit adder: bottom-up hierarchical description Digital Circuit Design 61

62 HDL Example 4-2 (2/2) Digital Circuit Design 62

63 Three-State Gates Digital Circuit Design Statement: gate name (output, input, control); 63

64 Three-State Gates Digital Circuit Design Examples of gate instantiation 64

65 65

66 Dataflow Modeling Verilog HDL operators Example: assign Y = (A & S) (B & ~S)

67 HDL Example 4.3 Digital Circuit Design Dataflow description of a 2-to-4-line decoder 67

68 HDL Example 4-4 Digital Circuit Design Dataflow description of 4-bit adder 68

69 HDL Example 4-5 Digital Circuit Design Dataflow description of 4-bit magnitude comparator 69

70 HDL Example 4-6 Dataflow description of a 2-to-1-line multiplexer Conditional operator (?:) Condition? True-expression : false-expression Example: continuous assignment assign OUT = select? A : B 70

71 Behavioral Modeling Digital Circuit Design if statement: if (select) OUT = A; HDL Example 4-7 Behavioral description of a 2-to-1-line multiplexer 71

72 HDL Example 4-8 Digital Circuit Design Behavioral description of a 4-to-1-line multiplexer 72

73 Writing a Simple Test Bench A stimulus module has the following form: 73

74 Writing a Simple Test Bench Interaction between stimulus and design modules Digital Circuit Design 74

75 Writing a Simple Test Bench Digital Circuit Design System tasks for display 75

76 Stimulus module (Example) HDL Example 4-9 Digital Circuit Design 76

77 HDL Example 4-9 (Continued) 77

78 Conclusion From this lecture, you have learned the follows: Adder/Subtractor Multiplier Decoder Encoder Multiplexer Verilog Design DCD-04-78

Combinational Logic. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

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