CprE 281: Digital Logic
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1 CprE 28: Digital Logic Instructor: Alexander Stoytchev
2 Decoders and Encoders CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 HW 6 is due today Administrative Stuff
4 HW 7 is out Administrative Stuff It is due next Monday (Oct 7)
5 Administrative Stuff Midterm Grades are Due this Friday only grades of C-, D, F have to be submitted to the registrar s office
6 Quick Review
7 Graphical Symbol for a 2- Multiplexer s x x 2 f [ Figure 2.33c from the textbook ]
8 Circuit for 2- Multiplexer x s s x 2 f x x 2 f (b) Circuit (c) Graphical symbol f (s, x, x 2 ) = s x + s x 2 [ Figure 2.33b-c from the textbook ]
9 The Three Basic Logic Gates x x x x x x 2 2 x x x + x 2 2 NOT gate AND gate OR gate [ Figure 2.8 from the textbook ]
10 Building an AND Gate with 2-to- Mux x 2
11 Building an OR Gate with 2-to- Mux x 2
12 Building a NOT Gate with 2-to- Mux x x x x
13 Implications Any Boolean function can be implemented using only 2-to- multiplexers!
14 4-to- Multiplexer: Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]
15 The Three Basic Logic Gates x x x x x x 2 2 x x x + x 2 2 NOT gate AND gate OR gate [ Figure 2.8 from the textbook ]
16 Building an AND Gate with 4-to- Mux
17 Building an OR Gate with 4-to- Mux
18 Building a NOT Gate with 4-to- Mux x x x x Two alternative solutions.
19 Implications Any Boolean function can be implemented using only 4-to- multiplexers!
20 Using three 2-to- multiplexers to build one 4-to- multiplexer s s w w f w 2 w 3 [ Figure 4.3 from the textbook ]
21 6- Multiplexer s s w w 3 w 4 s 2 s 3 w 7 f w 8 w w 2 w 5 [ Figure 4.4 from the textbook ]
22 Synthesis of Logic Circuits Using Multiplexers
23 Implementation of a logic function with a 4x multiplexer w w 2 f w 2 w f [ Figure 4.6a from the textbook ]
24 Implementation of the same logic function with a 2x multiplexer w w 2 f w f w 2 w 2 w 2 w f (b) Modified truth table (c) Circuit [ Figure 4.6b-c from the textbook ]
25 The XOR Logic Gate [ Figure 2. from the textbook ]
26 The XOR Logic Gate [ Figure 2. from the textbook ]
27 Implementation of the XOR Logic Gate with a 2-to- multiplexer and one NOT f
28 Implementation of the XOR Logic Gate with a 2-to- multiplexer and one NOT x y f
29 Implementation of the XOR Logic Gate with a 2-to- multiplexer and one NOT x y f These two circuits are equivalent (the wires of the bottom AND gate are flipped)
30 In other words, all four of these are equivalent! x y y f x f w 2 w x y f f
31 Another Example (3-input XOR)
32 Implementation of 3-input XOR with 2-to- Multiplexers w w 2 w 3 f [ Figure 4.8a from the textbook ]
33 Implementation of 3-input XOR with 2-to- Multiplexers w w 2 w 3 f w 2 w 3 w 2 w 3 [ Figure 4.8a from the textbook ]
34 Implementation of 3-input XOR with 2-to- Multiplexers w w 2 w 3 f w 2 w 3 w 2 w 3 w 2 w 3 w f (a) Truth table (b) Circuit [ Figure 4.8 from the textbook ]
35 Implementation of 3-input XOR with 2-to- Multiplexers w w 2 w 3 f w 3 w 3 w 3 w 2 w f (a) Truth table (b) Circuit [ Figure 4.8 from the textbook ]
36 Implementation of 3-input XOR with a 4-to- Multiplexer w w 2 w 3 f [ Figure 4.9a from the textbook ]
37 Implementation of 3-input XOR with a 4-to- Multiplexer w w 2 w 3 f [ Figure 4.9a from the textbook ]
38 Implementation of 3-input XOR with a 4-to- Multiplexer w w 2 w 3 f w 3 w 3 w 3 w 3 [ Figure 4.9a from the textbook ]
39 Implementation of 3-input XOR with a 4-to- Multiplexer w w 2 w 3 f w 3 w 3 w 3 w 2 w w 3 f w 3 (a) Truth table (b) Circuit [ Figure 4.9 from the textbook ]
40 Multiplexor Synthesis Using Shannon s Expansion
41 Three-input majority function w w 2 w 3 f [ Figure 4.a from the textbook ]
42 Three-input majority function w w 2 w 3 f w f [ Figure 4.a from the textbook ]
43 Three-input majority function w w 2 w 3 f w f w 2 w 3 w 2 + w 3 [ Figure 4.a from the textbook ]
44 Three-input majority function w w 2 w 3 f w f w 2 w 3 w 2 + w 3 (b) Truth table w w 2 w 3 f (b) Circuit [ Figure 4.a from the textbook ]
45 Three-input majority function w w 2 w 3 f
46 Shannon s Expansion Theorem Any Boolean function can be rewritten in the form:
47 Shannon s Expansion Theorem Any Boolean function can be rewritten in the form:
48 Shannon s Expansion Theorem Any Boolean function can be rewritten in the form: cofactor cofactor
49 Shannon s Expansion Theorem (Example)
50 Shannon s Expansion Theorem (Example) (w + w )
51 Shannon s Expansion Theorem (Example) (w + w )
52 Shannon s Expansion Theorem (In terms of more than one variable) This form is suitable for implementation with a 4x multiplexer.
53 Another Example
54 Factor and implement the following function with a 2x multiplexer
55 Factor and implement the following function with a 2x multiplexer
56 Factor and implement the following function with a 2x multiplexer w f [ Figure 4.a from the textbook ]
57 Factor and implement the following function with a 4x multiplexer
58 Factor and implement the following function with a 4x multiplexer
59 Factor and implement the following function with a 4x multiplexer [ Figure 4.b from the textbook ]
60 Yet Another Example
61 Factor and implement the following function using only 2x multiplexers
62 Factor and implement the following function using only 2x multiplexers
63 Factor and implement the following function using only 2x multiplexers
64 Factor and implement the following function using only 2x multiplexers w g h f
65 Factor and implement the following function using only 2x multiplexers
66 Factor and implement the following function using only 2x multiplexers
67 Factor and implement the following function using only 2x multiplexers w 2 w 2 w 3 g w 3 h
68 Finally, we are ready to draw the circuit w 2 w 3 w 2 g g h w f w 3 h
69 Finally, we are ready to draw the circuit w 2 w 3 g w f h
70 Finally, we are ready to draw the circuit w 2 w w 3 f [ Figure 4.2 from the textbook ]
71 Decoders
72 2-to-4 Decoder (Definition) Has two inputs: w and w Has four outputs: y, y, y 2, and y 3 If w = and w =, then the output y is set to If w = and w =, then the output y is set to If w = and w =, then the output y 2 is set to If w = and w =, then the output y 3 is set to Only one output is set to. All others are set to.
73 Truth Table and Graphical Symbol for a 2-to-4 Decoder [ Figure 4.3a-b from the textbook ]
74 Truth Logic Circuit for a 2-to-4 Decoder [ Figure 4.3c from the textbook ]
75 Adding an Enable Input [ Figure 4.3c from the textbook ]
76 Adding an Enable Input En [ Figure 4.3c from the textbook ]
77 Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input [ Figure 4.4a-b from the textbook ]
78 Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input x indicates that it does not matter what the value of this variable is for this row of the truth table [ Figure 4.4a-b from the textbook ]
79 Graphical Symbol for a Binary n-to-2 n Decoder with an Enable Input A binary decoder with n inputs has 2 n outputs The outputs of an enabled binary decoder are one-hot encoded, meaning that only a single bit is set to, i.e., it is hot. [ Figure 4.4d from the textbook ]
80 How can we build larger decoders? 3-to-8? 4-to-6? 5-to-??
81 Hint: How did we build a 6- Multiplexer s s w w 3 w 4 s 2 s 3 w 7 f w 8 w w 2 w 5 [ Figure 4.4 from the textbook ]
82 A 3-to-8 decoder using two 2-to-4 decoders w y w y w w 2 w y y 2 En y 3 y y 2 y 3 En w y y 4 w y y 2 En y 3 y 5 y 6 y 7 [ Figure 4.5 from the textbook ]
83 A 3-to-8 decoder using two 2-to-4 decoders w y w y w w 2 w y y 2 En y 3 y y 2 y 3 En w y y 4 w y y 2 En y 3 y 5 y 6 y 7 What is this? [ Figure 4.5 from the textbook ]
84 What is this? w y En y
85 A 4-to-6 decoder built using a decoder tree w w y y w w y y En y 2 y 3 y 2 y 3 w 2 w 3 En w y w y En y 2 y 3 w w y En y 2 y 3 w y y w w y En y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y y [ Figure 4.6 from the textbook ] w y w y En y 2 y 3 y 2 y 3 y 4 y 5
86 Let s build a 5-to-32 decoder
87 Let s build a 5-to-32 decoder y y 5 En y 6 y 3
88 Let s build a 5-to-32 decoder w w w 2 w 3 y y 5 w 4 En w w w 2 w 3 y 6 y 3
89 Demultiplexers
90 -to-4 Demultiplexer (Definition) Has one data input line: D Has two output select lines: w and w Has four outputs: y, y, y 2, and y 3 If w = and w =, then the output y is set to D If w = and w =, then the output y is set to D If w = and w =, then the output y 2 is set to D If w = and w =, then the output y 3 is set to D Only one output is set to D. All others are set to.
91 A -to-4 demultiplexer built with a 2-to-4 decoder [ Figure 4.4c from the textbook ]
92 A -to-4 demultiplexer built with a 2-to-4 decoder output select lines the four output lines data input line D [ Figure 4.4c from the textbook ]
93 Multiplexers (Implemented with Decoders)
94 A 4-to- multiplexer built using a 2-to-4 decoder w w s s w y w y En y 2 y 3 w 2 f w 3 [ Figure 4.7 from the textbook ]
95 Encoders
96 Binary Encoders
97 A 2 n -to-n binary encoder 2 n inputs w w 2 n y y n n outputs [ Figure 4.8 from the textbook ]
98 A 4-to-2 binary encoder w 3 w 2 w w y y (a) Truth table w w y w 2 w 3 y (b) Circuit [ Figure 4.9 from the textbook ]
99 A 4-to-2 binary encoder w 3 w 2 w w y y (a) Truth table w? w y w 2 w 3 y (b) Circuit [ Figure 4.9 from the textbook ]
100 A 4-to-2 binary encoder w 3 w 2 w w y y (a) Truth table w It is assumed that the inputs are one hot encoded w y w 2 w 3 y (b) Circuit [ Figure 4.9 from the textbook ]
101 Priority Encoders
102 d w y d y z x x x w x x w 2 x w 3 [ Figure 4.2 from the textbook ] Truth table for a 4-to-2 priority encoder
103 Questions?
104 THE END
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