COSC3330 Computer Architecture Lecture 2. Combinational Logic


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1 COSC333 Computer rchitecture Lecture 2. Combinational Logic Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston
2 Today Combinational Logic oolean lgebra Mux, DeMux, Decoder
3 Extra Credit Question Thanks for all who submitted
4 Z Konrad Zuse: the Z (938), Germany First binary programmable computer, completely mechanical Punchcard input, processing implemented with metal plates Konrad designed the first high level programming language 4
5 Zoomin a System Component
6 Circuit logic circuit is composed of Inputs Outputs Functional specification Relationship between inputs and outputs Timing specification Delay from inputs to outputs inputs functional spec timing spec outputs 6
7 Circuits Nodes Inputs:,, C Outputs: Y, Z Internal: n Circuit elements E, E2, E3 E n E3 Y C E2 Z 7
8 Types of Logic Circuits Combinational Logic Outputs are determined by current values of inputs Thus, it is memoryless Sequential Logic Outputs are determined by previous and current values of inputs Thus, it has memory inputs functional spec timing spec outputs 8
9 Rules of Combinational Composition circuit is combinational if Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element The circuit contains no cyclic paths Every path through the circuit visits each circuit node at most once Every circuit element is itself combinational Select combinational logic? 9
10 oolean Equations The functional specification of a combination logic is usually expressed as a truth table or a oolean equation Truth table is in a tabular form oolean equation is in a algebraic form Example: S = F(,, C in ) C out = F(,, C in ) Truth Table oolean equation
11 Terminology The complement of a variable is variable or its complement is called literal ND of one or more literals is called a product or implicant Example:, C, OR of one or more literals is called a sum Example: + Order of operations NOT has the highest precedence, followed by ND, then OR Example: Y = + C
12 Minterms minterm is a product (ND) of literals involving all of the inputs to the function Each row in a truth table has a minterm that is true for that row (and only that row) 2
13 SumofProducts (SOP) Form The function is formed by ORing the minterms for which the output is true Thus, a sum (OR) of products (ND terms) ll oolean equations can be written in SOP form Y minterm Y = F(, ) = + 3
14 oolean lgebra George oole We learned how to write a boolean equation given a truth table ut, that expression does not necessarily lead to the simplest set of logic gates One way to simplify boolean equations is to use boolean algebra Set of theorems It is like regular algebra, but in some cases simpler because variables can have only two values ( or ) Theorems obey the principles of duality: NDs and ORs interchanged, s and s interchanged 4
15 oolean Theorems of One Variable The prime ( ) symbol denotes the dual of a statement 5
16 oolean Theorems of One Variable T: Identity Theorem = + = = = T2: Null Element Theorem = + = = = 6
17 oolean Theorems of One Variable Idempotency Theorem = + = = = T4: Identity Theorem = = T5: Complement Theorem = + = = = 7
18 oolean Theorems of Several Variables 8
19 Simplifying oolean Expressions: Example Y = + = ( + ) T8 = () T5 = T 9
20 Simplifying oolean Expressions: Example 2 Y = ( + C) = ( ( + C)) T8 = ( ()) T2 = () T = () T7 = T3 2
21 DeMorgan s Theorem Powerful theorem in digital design Y = = + Y + Y Y = + = + Y Y 2
22 DeMorgan s Theorem
23 ubble Pushing Pushing bubbles backward (from the output) or forward (from the inputs) changes the body of the gate from ND to OR or vice versa Pushing a bubble from the output back to the inputs puts bubbles on all gate inputs Y Y Pushing bubbles on all gate inputs forward toward the output puts a bubble on the output and changes the gate body Y Y 23
24 ubble Pushing What is the oolean expression for this circuit? C D Y C D Y Y = + CD 24
25 Universal Gate gate which can be use to create any Logic gate. Two universal gates NND NOR 25
26 NOR as Universal Gate 26
27 From Logic to Gates Schematic diagram of a digital circuit showing the elements and the wires that connect them together Example: Y = C + C + C C C minterm: C minterm: C minterm: C ny oolean equation in the SOP form can be drawn like above Y 27
28 Circuit Schematic Rules Inputs are on the left (or top) side of a schematic Outputs are on the right (or bottom) side of a schematic Whenever possible, gates should flow from left to right Straight wires are better to use than wires with multiple corners C C minterm: C minterm: C minterm: C 28 Y
29 Circuit Schematic Rules (cont.) Wires always connect at a T junction dot where wires cross indicates a connection between the wires Wires crossing without a dot make no connection wires connect at a T junction wires connect at a dot wires crossing without a dot do not connect 29
30 Multiple Output Circuits 3 2 Y 3 Y 2 Y Y 3 2 Y 3 Y 2 Y Y 3
31 Don t Cares (X) 3 2 Y 3 Y 2 Y Y 3 2 X X X X Y 3 Y 2 Y Y X X Y 3 = 3 Y 2 = 3 2 Y = 3 2 Y = 3 2 3
32 Floating: Z Output is disconnected from the input if not enabled We say output is floating, high impedance, open, or high Z Tristate uffer E n implementation Example Y E Y Z Z 32
33 Where Is Tristate uffer Used for? Tristate buffer is used when designing hardware components sharing a communication medium called shared bus Many hardware components can be attached on a shared bus Only one component is allowed to drive the bus at a time The other components put their outputs to the floating What happen if you don t use the tristate buffer on shared bus? Hardware Device Hardware Device Hardware Device 2 shared bus Hardware Device 3 Hardware Device 4 Hardware Device 5 33
34 Timing There is always delay from input change to output change in real world One of the biggest challenges in circuit design is to make the circuit fast Y delay Y Time 34
35 Propagation & Contamination Delay Propagation delay t pd = max delay from input to output Contamination delay t cd = min delay for a change at the input to affect the output 35
36 Propagation & Contamination Delay Delay is caused by Transistor capacitance and resistance in a circuit Interconnection capacitance and resistance Reasons why t pd and t cd may be different Different rising and falling delays Multiple inputs and outputs, some of which are faster than others Circuits speeds are different depending on temperature Circuit slows down when hot Circuit speeds up when cold 36
37 Critical and Short Paths Critical Path C D n Short Path n2 Y Critical (Longest) Path: t pd = 2t pd_nd + t pd_or Short Path: t cd = t cd_nd 37
38 Digital Components Digital Components Mux Demux Decoder
39 Recap: SumofProducts (SOP) Form The function is formed by ORing the minterms for which the output is true Thus, a sum (OR) of products (ND terms) ll oolean equations can be written in SOP form Y minterm Y = F(, ) = + 39
40 Combinational uilding locks Combinational logic is often grouped into larger building blocks to build more complex systems 2 other very commonly used digital components Multiplexers Decoders 4
41 Multiplexer (Mux) Multiplexer selects an output from inputs based on the value of a select signal Multiplexer is many times called a mux Example: 2: Mux S D D Y Y = S D D + S D D + S D D +S D D = S D (D +D )+ S D (D +D ) = S D + S D S Y D D 4
42 Wider Muxes 4: Mux 4 inputs, output, and 2 select signals 8: Mux 8 inputs, output, and 3 select signals 6: Mux 6 inputs, output, and 4 select signal N: Mux N inputs, output, and log 2 N select signals 42
43 Multiplexers (Mux) 2 En 4to Mux 3 S S F Functionality: Selection of a particular input Route of N inputs () to the output F Require bits (S) N log 2 selection En(able) bit can disable the route and set F to
44 Multiplexers (Mux) w/out Enable S S F 2 4to Mux F 2 3 S S 3 F S S SS SS 2 SS3
45 Gate Diagram F S S S S S S S 2 3 S S S
46 4to Mux Input nalysis 2 3 S S : Mux S S F 2 3
47 Multiplexers (Mux) w/ Enable En En S S F X X 2 4to Mux F 3 S S 2 3 F En EnSS (SS SS EnSS SS2 S EnSS2 S 3) EnS S 3
48 4to Mux w/ Enable Logic S S F En (SS SS SS2 3 S F S ) 2 3 En
49 4to Mux w/ Enable Logic F EnS S EnS S EnS S EnS 2 3 S S S F 2 Reduce one Gate Delay by using 4input ND gate for the 2 nd level 3 En
50 Real Multiplexer Chip 5
51 Demultiplexers (DeMux) D 2 4to Mux F to4 DeMux D D 2 3 S S S S D 3
52 DeMux Operations S S D3 D2 D D D to4 DeMux S S D D 2 D 3 D D S S S S D D 2 3 S S S S
53 DeMux Operations S S D D S S D3 D2 D D D2 D3 D D D D 2 3 S S S S SS S S
54 DeMux Input nalysis D D D2 D3 D D D2 D3 S S D3 D2 D D
55 DeMux Operations w/ Enable S S D D D2 D3 En S S D3 D2 D D X X En
56 Decoders Decoder asserts only one of outputs depending on the input combination N inputs, 2 N outputs Onehot because only one output is hot (HIGH) at a given time 56
57 Logic using Decoders Decoders can be combined with OR gates to build logic functions SOP form (ORing minterms) 2:4 Decoder Y = Y Minterm 57
58 Real Decoder Chip 74LS38 3 inputs, 8 outputs inputs outputs 58
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