Combinational logic. Possible logic functions of two variables. Minimal set of functions. Cost of different logic functions.

Transcription

1 Combinational logic Possible logic functions of two variables Logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,... Minimal set xioms and theorems of oolean algebra Proofs by re-writing Proofs by perfect induction Gate logic Networks of oolean functions Time behavior Canonical forms Two-level Incompletely specified functions 16 possible functions of 2 input variables: 2**(2**n) functions of n inputs 16 possible functions (F0 F15) and xor or F = nor not ( or ) not not 1 nand not ( and ) CS Spring 2004 Lec #2: Transistor & Gate Logic - 1 CS Spring 2004 Lec #2: Transistor & Gate Logic - 2 Cost of different logic functions Minimal set of functions Some are easier, others harder, to implement Each has a cost associated with the number of switches needed 0 (F0) and 1 (F15): require 0 switches, directly connect output to low/high (F3) and (F5): require 0 switches, output is one of inputs ' (F12) and ' (F10): require 2 switches for "inverter" or NOT-gate nor (F4) and nand (F14): require 4 switches or (F7) and and (F1): require 6 switches = (F9) and (F6): require 16 switches ecause NOT, NOR, and NND are the cheapest they are the functions we implement the most in practice CS Spring 2004 Lec #2: Transistor & Gate Logic - 3 Implement any logic functions from NOT, NOR, and NND? For example, implementing and is the same as implementing not ( nand ) Do it with only NOR or only NND NOT is just a NND or a NOR with both inputs tied together nor nand and NND and NOR are "duals", i.e., easy to implement one using the other nand not ( (not ) nor (not ) ) nor not ( (not ) nand (not ) ) ased on the mathematical foundations of logic: oolean lgebra CS Spring 2004 Lec #2: Transistor & Gate Logic - 4 n algebraic structure oolean algebra n algebraic structure consists of a set of elements binary operations { +, } and a unary operation { ' } such that the following axioms hold: oolean algebra = {0, 1} + is logical OR, is logical ND ' is logical NOT ll algebraic axioms hold 1. set contains at least two elements, a, b, such that a b 2. closure: a + b is in a b is in 3. commutativity: a + b = b + a a b = b a 4. associativity: a + (b + c) = (a + b) + c a (b c) = (a b) c 5. identity: a + 0 = a a 1 = a 6. distributivity: a + (b c) = (a + b) (a + c) a (b + c) = (a b) + (a c) 7. complementarity: a + a' = 1 a a' = 0 CS Spring 2004 Lec #2: Transistor & Gate Logic - 5 CS Spring 2004 Lec #2: Transistor & Gate Logic - 6

2 Logic functions and oolean algebra ny logic function that can be expressed as a truth table can be written as an expression in oolean algebra using the operators: ', +, and xioms and theorems of oolean algebra Identity = 1D. 1 = Null = 1 2D. 0 = 0 ' ' Idempotency: 3. + = 3D. = Involution: 4. (')' = ' ' ' ' ( ) + ( ' ' ) ( ) + ( ' ' ) $ = oolean expression that is true when the variables and have the same value, are oolean algebra variables and false, otherwise CS Spring 2004 Lec #2: Transistor & Gate Logic - 7 Complementarity: 5. + ' = 1 5D. ' = 0 Commutativity: 6. + = + 6D. = ssociativity: 7. ( + ) + = + ( + ) 7D. ( ) = ( ) CS Spring 2004 Lec #2: Transistor & Gate Logic - 8 xioms and theorems of oolean algebra (cont d) xioms and theorems of oolean algebra (cont ) Distributivity: 8. ( + ) = ( ) + ( ) 8D. + ( ) = ( + ) ( + ) Uniting: 9. + ' = 9D. ( + ) ( + ') = bsorption: = 10D. ( + ) = 11. ( + ') = 11D. ( ') + = + Factoring: 12. ( + ) (' + ) = 12D. + ' = + ' ( + ) (' + ) de Morgan's: 14. ( )' = ' '... 14D. (...)' = ' + ' +... generalized de Morgan's: 15. f'(1,2,...,n,0,1,+, ) = f(1',2',...,n',1,0,,+) establishes relationship between and + Concensus: 13. ( ) + ( ) + (' ) = 17D. ( + ) ( + ) (' + ) = + ' ( + ) (' + ) CS Spring 2004 Lec #2: Transistor & Gate Logic - 9 CS Spring 2004 Lec #2: Transistor & Gate Logic - 10 xioms and theorems of oolean algebra (cont ) Proving theorems (rewriting) Duality Dual of a oolean expression is derived by replacing by +, + by, 0 by 1, and 1 by 0, and leaving variables unchanged ny theorem that can be proven is thus also proven for its dual! Meta-theorem (a theorem about theorems) duality: Using the axioms of oolean algebra: e.g., prove the theorem: + ' = distributivity (8) + ' = ( + ') complementarity (5) ( + ') = (1) identity (1D) (1) = generalized duality: 17. f (1,2,...,n,0,1,+, ) f(1,2,...,n,1,0,,+) Different than demorgan s Law this is a statement about theorems this is not a way to manipulate (re-write) expressions CS Spring 2004 Lec #2: Transistor & Gate Logic - 11 e.g., prove the theorem: + = identity (1D) + = 1 + distributivity (8) 1 + = (1 + ) identity (2) (1 + ) = (1) identity (1D) (1) = CS Spring 2004 Lec #2: Transistor & Gate Logic - 12

3 Proving theorems (perfect induction) simple example Using perfect induction (complete truth table): e.g., de Morgan's: ( + )' = ' ' NOR is equivalent to ND with inputs complemented ( )' = ' + ' NND is equivalent to OR with inputs complemented ' ' ( + )' ' ' ' ' ( )' ' + ' bit binary adder inputs:,, Carry-in outputs: Sum, Carry-out Cin S Cout Cin S Cout S = ' ' Cin + ' Cin' + ' Cin' + Cin Cout = ' Cin + ' Cin + Cin' + Cin CS Spring 2004 Lec #2: Transistor & Gate Logic - 13 CS Spring 2004 Lec #2: Transistor & Gate Logic - 14 pply the theorems to simplify expressions From oolean expressions to logic gates The theorems of oolean algebra can simplify oolean expressions e.g., full adder's carry-out function (same rules apply to any function) Cout = ' Cin + ' Cin + Cin' + Cin = ' Cin + ' Cin + Cin' + Cin + Cin = ' Cin + Cin + ' Cin + Cin' + Cin = (' + ) Cin + ' Cin + Cin' + Cin = (1) Cin + ' Cin + Cin' + Cin = Cin + ' Cin + Cin' + Cin + Cin = Cin + ' Cin + Cin + Cin' + Cin = Cin + (' + ) Cin + Cin' + Cin = Cin + (1) Cin + Cin' + Cin = Cin + Cin + (Cin' + Cin) = Cin + Cin + (1) = Cin + Cin + NOT ' ~ ND OR CS Spring 2004 Lec #2: Transistor & Gate Logic - 15 CS Spring 2004 Lec #2: Transistor & Gate Logic - 16 From oolean expressions to logic gates (cont d) From oolean expressions to logic gates (cont d) NND NOR OR NOR = xor = ' + ' or but not both ("inequality", "difference") xnor = + ' ' and are the same ("equality", "coincidence") More than one way to map expressions to gates T2 e.g., = ' ' (C + D) = (' (' (C + D))) T1 C D T2 T1 C D use of 3-input gate CS Spring 2004 Lec #2: Transistor & Gate Logic - 17 CS Spring 2004 Lec #2: Transistor & Gate Logic - 18

4 Waveform view of logic functions Choosing different realizations of a function Just a sideways truth table but note how edges don't line up exactly it takes time for a gate to switch its output! time C two-level realization (we don't count NOT gates) multi-level realization (gates with fewer inputs) change in takes time to "propagate" through gates OR gate (easier to draw but costlier to build) CS Spring 2004 Lec #2: Transistor & Gate Logic - 19 CS Spring 2004 Lec #2: Transistor & Gate Logic - 20 Which realization is best? Which is the best realization? (cont d) Reduce number of inputs literal: input variable (complemented or not) can approximate cost of logic gate as 2 transistors per literal why not count inverters? Fewer literals means less transistors smaller circuits Fewer inputs implies faster gates gates are smaller and thus also faster Fan-ins (# of gate inputs) are limited in some technologies Reduce number of gates Fewer gates (and the packages they come in) means smaller circuits directly influences manufacturing costs Reduce number of levels of gates Fewer level of gates implies reduced signal propagation delays Minimum delay configuration typically requires more gates wider, less deep circuits How do we explore tradeoffs between increased circuit delay and size? utomated tools to generate different solutions Logic minimization: reduce number of gates and complexity Logic optimization: reduction while trading off against delay CS Spring 2004 Lec #2: Transistor & Gate Logic - 21 CS Spring 2004 Lec #2: Transistor & Gate Logic - 22 re all realizations equivalent? Implementing oolean functions Under the same inputs, the alternative implementations have almost the same waveform behavior delays are different glitches (hazards) may arise variations due to differences in number of gate levels and structure Three implementations are functionally equivalent Technology independent Canonical forms Two-level forms Multi-level forms Technology choices Packages of a few gates Regular logic Two-level programmable logic Multi-level programmable logic CS Spring 2004 Lec #2: Transistor & Gate Logic - 23 CS Spring 2004 Lec #2: Transistor & Gate Logic - 24

5 Canonical forms Sum-of-products canonical forms Truth table is the unique signature of a oolean function Many alternative gate realizations may have the same truth table Canonical forms Standard forms for a oolean expression Provides a unique algebraic signature lso known as disjunctive normal form lso known as minterm expansion C F F' F = F = ''C+ 'C + 'C + C' + C F' = ''C' + 'C' + 'C' CS Spring 2004 Lec #2: Transistor & Gate Logic - 25 CS Spring 2004 Lec #2: Transistor & Gate Logic - 26 Sum-of-products canonical form (cont d) Product-of-sums canonical form Product term (or minterm) NDed product of literals input combination for which output is true Each variable appears exactly once, in true or inverted form (but not both) C minterms ''C'm0 ''C m1 'C' m 'C m3 'C' m 'C m5 C' m6 C m7 short-hand notation for minterms of 3 variables F in canonical form: F(,, C) = Σm(1,3,5,6,7) = m1 + m3 + m5 + m6 + m7 = ''C + 'C + 'C + C' + C canonical form minimal form F(,, C) = ''C + 'C + 'C + C + C' = ('' + ' + ' + )C + C' = ((' + )(' + ))C + C' = C + C' = C' + C = + C CS Spring 2004 Lec #2: Transistor & Gate Logic - 27 lso known as conjunctive normal form lso known as maxterm expansion C F F' F = F = ( + + C) ( + ' + C) (' + + C) F' = ( + + C') ( + ' + C') (' + + C') (' + ' + C) (' + ' + C') CS Spring 2004 Lec #2: Transistor & Gate Logic - 28 Product-of-sums canonical form (cont d) S-o-P, P-o-S, and de Morgan s theorem Sum term (or maxterm) ORed sum of literals input combination for which output is false each variable appears exactly once, in true or inverted form (but not both) C maxterms ++C M0 ++C' M1 +'+C M '+C' M3 '++C M '++C' M5 '+'+C M6 '+'+C' M7 short-hand notation for maxterms of 3 variables F in canonical form: F(,, C) = ΠM(0,2,4) = M0 M2 M4 = ( + + C) ( + ' + C) (' + + C) canonical form minimal form F(,, C) = ( + + C) ( + ' + C) (' + + C) = ( + + C) ( + ' + C) ( + + C) (' + + C) = ( + C) ( + C) CS Spring 2004 Lec #2: Transistor & Gate Logic - 29 Sum-of-products F' = ''C' + 'C' + 'C' pply de Morgan's (F')' = (''C' + 'C' + 'C')' F = ( + + C) ( + ' + C) (' + + C) Product-of-sums F' = ( + + C') ( + ' + C') (' + + C') (' + ' + C) (' + ' + C') pply de Morgan's (F')' = ( ( + + C')( + ' + C')(' + + C')(' + ' + C)(' + ' + C') )' F = ''C + 'C + 'C + C' + C CS Spring 2004 Lec #2: Transistor & Gate Logic - 30

6 Four alternative two-level implementations of F = + C Waveforms for the four alternatives F1 canonical sum-of-products Waveforms are essentially identical Except for timing hazards (glitches) Delays almost identical (modeled as a delay per level, not type of gate or number of inputs to gate) C minimized sum-of-products F2 canonical product-of-sums F3 minimized product-of-sums F4 CS Spring 2004 Lec #2: Transistor & Gate Logic - 31 CS Spring 2004 Lec #2: Transistor & Gate Logic - 32 Mapping between canonical forms Incompleteley specified functions Minterm to maxterm conversion Use maxterms whose indices do not appear in minterm expansion e.g., F(,,C) = Σm(1,3,5,6,7) = ΠM(0,2,4) Maxterm to minterm conversion Use minterms whose indices do not appear in maxterm expansion e.g., F(,,C) = ΠM(0,2,4) = Σm(1,3,5,6,7) Minterm expansion of F to minterm expansion of F' Use minterms whose indices do not appear e.g., F(,,C) = Σm(1,3,5,6,7) F'(,,C) = Σm(0,2,4) Maxterm expansion of F to maxterm expansion of F' Use maxterms whose indices do not appear e.g., F(,,C) = ΠM(0,2,4) F'(,,C) = ΠM(1,3,5,6,7) Example: binary coded decimal increment by 1 CD digits encode decimal digits 0 9 in bit patterns C D W off-set of W on-set of W don't care (DC) set of W these inputs patterns should never be encountered in practice "don't care" about associated output values, can be exploited in minimization CS Spring 2004 Lec #2: Transistor & Gate Logic - 33 CS Spring 2004 Lec #2: Transistor & Gate Logic - 34 Notation for incompletely specified functions Simplification of two-level combinational logic Don't cares and canonical forms So far, only represented on-set lso represent don't-care-set Need two of the three sets (on-set, off-set, dc-set) Canonical representations of the CD increment by 1 function: = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 + d15 = Σ [ m(0,2,4,6,8) + d(10,11,12,13,14,15) ] = M1 M3 M5 M7 M9 D10 D11 D12 D13 D14 D15 = Π [ M(1,3,5,7,9) D(10,11,12,13,14,15) ] CS Spring 2004 Lec #2: Transistor & Gate Logic - 35 Finding a minimal sum of products or product of sums realization Exploit don't care information in the process lgebraic simplification Not an algorithmic/systematic procedure How do you know when the minimum realization has been found? Computer-aided design tools Precise solutions require very long computation times, especially for functions with many inputs (> 10) Heuristic methods employed "educated guesses" to reduce amount of computation and yield good if not best solutions Hand methods still relevant To understand automatic tools and their strengths and weaknesses bility to check results (on small examples) CS Spring 2004 Lec #2: Transistor & Gate Logic - 36

7 Combinational logic summary Logic functions, truth tables, and switches NOT, ND, OR, NND, NOR, OR,..., minimal set xioms and theorems of oolean algebra Proofs by re-writing and perfect induction Gate logic Networks of oolean functions and their time behavior Canonical forms Two-level and incompletely specified functions Later Two-level simplification using K-maps utomation of simplification Multi-level logic Design case studies Time behavior CS Spring 2004 Lec #2: Transistor & Gate Logic - 37